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hal/nrf24l01p/hal_nrf.c

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00001 /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
00002  *
00003  * The information contained herein is confidential property of Nordic
00004  * Semiconductor ASA.Terms and conditions of usage are described in detail
00005  * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
00006  *
00007  * Licensees are granted free, non-transferable use of the information. NO
00008  * WARRENTY of ANY KIND is provided. This heading must NOT be removed from
00009  * the file.
00010  *
00011  * $LastChangedRevision: 2713 $
00012  */
00013 
00017 /*lint -t2 */
00018 /*lint -esym( 534, hal_nrf_write_reg ) */
00019 /*lint -esym( 534, hal_nrf_rw ) */
00020 /*lint -e708 */
00021 /*lint -e46 */
00022 
00023 #include <stdint.h>
00024 #include <stdbool.h>
00025 
00026 #include "nordic_common.h"
00027 #include "hal_nrf.h"
00028 
00029 #define SET_BIT(pos) ((uint8_t) (1U<<( (uint8_t) (pos) )))
00030 #define UINT8(t) ((uint8_t) (t))
00031 
00039 uint8_t hal_nrf_read_reg(uint8_t reg);
00040 
00049 uint8_t hal_nrf_write_reg(uint8_t reg, uint8_t value);
00050 
00062 uint16_t hal_nrf_read_multibyte_reg(uint8_t reg, uint8_t *pbuf);
00063 
00072 void hal_nrf_write_multibyte_reg(uint8_t reg, const uint8_t *pbuf, uint8_t length);
00073 
00078 typedef union {
00079   uint8_t value;
00080     struct {
00081         uint8_t prim_rx : 1;
00082         uint8_t pwr_up : 1;
00083         uint8_t crc0 : 1;
00084         uint8_t en_crc : 1;
00085         uint8_t mask_max_rt : 1;
00086         uint8_t mask_tx_ds : 1;
00087         uint8_t mask_rx_dr : 1;
00088         const uint8_t : 1;
00089     } bits;
00090 } config_t;
00091 
00097 typedef union {
00098   uint8_t value;
00099   struct {
00100     uint8_t pipe_0 : 1;
00101     uint8_t pipe_1 : 1;
00102     uint8_t pipe_2 : 1;
00103     uint8_t pipe_3 : 1;
00104     uint8_t pipe_4 : 1;
00105     uint8_t pipe_5 : 1;
00106     const uint8_t : 2;
00107   } bits;
00108 } en_pipes_t;
00109 
00114 typedef union {
00115   uint8_t value;
00116     struct {
00117         uint8_t aw : 2;
00118         const uint8_t : 6;
00119     } bits;
00120 } setup_aw_t;
00121 
00126 typedef union {
00127   uint8_t value;
00128     struct {
00129         uint8_t arc : 4;
00130         uint8_t ard : 4;
00131     } bits;
00132 } setup_retr_t;
00133 
00138 typedef union {
00139   uint8_t value;
00140     struct {
00141         uint8_t rf_ch : 7;
00142         const uint8_t : 1;
00143     } bits;
00144 } rf_ch_t;
00145 
00150 typedef union {
00151   uint8_t value;
00152     struct {
00153         const uint8_t : 1;
00154         uint8_t rf_pwr : 2;
00155         uint8_t rf_dr_high : 1;
00156         uint8_t pll_lock : 1;
00157         uint8_t rf_dr_low : 1;
00158     const uint8_t : 1;
00159     uint8_t cont_wave : 1;
00160     } bits;
00161 } rf_setup_t;
00162 
00167 typedef union {
00168   uint8_t value;
00169     struct {
00170         uint8_t rx_pw : 6;
00171         const uint8_t : 2;
00172     } bits;
00173 } rx_pw_t;
00174 
00179 typedef union {
00180   uint8_t value;
00181     struct {
00182         uint8_t en_dyn_ack : 1;
00183         uint8_t en_ack_pay : 1;
00184         uint8_t en_dpl : 1;
00185         const uint8_t : 5;
00186     } bits;
00187 } feature_t;
00188 
00189 void hal_nrf_set_operation_mode(hal_nrf_operation_mode_t op_mode)
00190 {
00191   config_t config;
00192   config.value = hal_nrf_read_reg (CONFIG);
00193 
00194   if(op_mode == HAL_NRF_PRX)
00195   {
00196     config.bits.prim_rx = 1U;
00197   }
00198   else
00199   {
00200     config.bits.prim_rx = 0U;
00201   }
00202 
00203   hal_nrf_write_reg (CONFIG, config.value);
00204 }
00205 
00206 void hal_nrf_set_power_mode(hal_nrf_pwr_mode_t pwr_mode)
00207 {
00208   config_t config;
00209   config.value = hal_nrf_read_reg (CONFIG);
00210 
00211   if(pwr_mode == HAL_NRF_PWR_UP)
00212   {
00213     config.bits.pwr_up = 1U;
00214   }
00215   else
00216   {
00217     config.bits.pwr_up = 0U;
00218   }
00219 
00220   hal_nrf_write_reg (CONFIG, config.value);
00221 }
00222 
00223 void hal_nrf_set_crc_mode(hal_nrf_crc_mode_t crc_mode)
00224 {
00225   config_t config;
00226   config.value = hal_nrf_read_reg (CONFIG);
00227 
00228     switch (crc_mode)
00229     {
00230         case HAL_NRF_CRC_OFF:
00231             config.bits.en_crc = 0U;
00232             break;
00233         case HAL_NRF_CRC_8BIT:
00234             config.bits.en_crc = 1U;
00235             config.bits.crc0 = 0U;
00236             break;
00237         case HAL_NRF_CRC_16BIT:
00238             config.bits.en_crc = 1U;
00239             config.bits.crc0 = 1U;
00240             break;
00241         default:
00242             break;
00243     }
00244 
00245   hal_nrf_write_reg (CONFIG, config.value);
00246 }
00247 
00248 void hal_nrf_set_irq_mode(hal_nrf_irq_source_t int_source, bool irq_state)
00249 {
00250   config_t config;
00251   config.value = hal_nrf_read_reg (CONFIG);
00252 
00253     switch (int_source)
00254     {
00255         case HAL_NRF_MAX_RT:
00256             config.bits.mask_max_rt = irq_state ? 0U : 1U;
00257       break;
00258     case HAL_NRF_TX_DS:
00259       config.bits.mask_tx_ds = irq_state ? 0U : 1U;
00260       break;
00261     case HAL_NRF_RX_DR:
00262       config.bits.mask_rx_dr = irq_state ? 0U : 1U;
00263       break;
00264   }
00265 
00266   hal_nrf_write_reg (CONFIG, config.value);
00267 }
00268 
00269 uint8_t hal_nrf_get_clear_irq_flags(void)
00270 {
00271   uint8_t retval;
00272 
00273   retval = hal_nrf_write_reg (STATUS, (BIT_6|BIT_5|BIT_4));
00274 
00275   return (retval & (BIT_6|BIT_5|BIT_4));
00276 }
00277 
00278 uint8_t hal_nrf_clear_irq_flags_get_status(void)
00279 {
00280   uint8_t retval;
00281 
00282   // When RFIRQ is cleared (when calling write_reg), pipe information is unreliable (read again with read_reg)
00283   retval = hal_nrf_write_reg (STATUS, (BIT_6|BIT_5|BIT_4)) & (BIT_6|BIT_5|BIT_4);
00284   retval |= hal_nrf_read_reg (STATUS) & (BIT_3|BIT_2|BIT_1|BIT_0);
00285 
00286   return (retval);
00287 }
00288 
00289 
00290 void hal_nrf_clear_irq_flag(hal_nrf_irq_source_t int_source)
00291 {
00292   hal_nrf_write_reg (STATUS, SET_BIT(int_source));
00293 }
00294 
00295 uint8_t hal_nrf_get_irq_flags(void)
00296 {
00297   return hal_nrf_nop() & (BIT_6|BIT_5|BIT_4);
00298 }
00299 
00300 void hal_nrf_open_pipe(hal_nrf_address_t pipe_num, bool auto_ack)
00301 {
00302   en_pipes_t en_rxaddr;
00303   en_pipes_t en_aa;
00304   en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
00305   en_aa.value = hal_nrf_read_reg (EN_AA);
00306 
00307   switch(pipe_num)
00308   {
00309     case HAL_NRF_PIPE0:
00310     case HAL_NRF_PIPE1:
00311     case HAL_NRF_PIPE2:
00312     case HAL_NRF_PIPE3:
00313     case HAL_NRF_PIPE4:
00314     case HAL_NRF_PIPE5:
00315       en_rxaddr.value = en_rxaddr.value | SET_BIT(pipe_num);
00316 
00317       if(auto_ack)
00318       {
00319         en_aa.value = en_aa.value | SET_BIT(pipe_num);
00320       }
00321       else
00322       {
00323         en_aa.value = en_aa.value & (uint8_t)~SET_BIT(pipe_num);
00324       }
00325       break;
00326 
00327     case HAL_NRF_ALL:
00328       en_rxaddr.value = (uint8_t)(~(BIT_6|BIT_7));
00329 
00330       if(auto_ack)
00331       {
00332         en_aa.value = (uint8_t)(~(BIT_6|BIT_7));
00333       }
00334       else
00335       {
00336         en_aa.value = 0U;
00337       }
00338       break;
00339 
00340     case HAL_NRF_TX:
00341     default:
00342       break;
00343   }
00344 
00345   hal_nrf_write_reg (EN_RXADDR, en_rxaddr.value);
00346   hal_nrf_write_reg (EN_AA, en_aa.value);
00347 }
00348 
00349 void hal_nrf_close_pipe(hal_nrf_address_t pipe_num)
00350 {
00351   en_pipes_t en_rxaddr;
00352   en_pipes_t en_aa;
00353   en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
00354   en_aa.value = hal_nrf_read_reg (EN_AA);
00355 
00356   switch(pipe_num)
00357   {
00358     case HAL_NRF_PIPE0:
00359     case HAL_NRF_PIPE1:
00360     case HAL_NRF_PIPE2:
00361     case HAL_NRF_PIPE3:
00362     case HAL_NRF_PIPE4:
00363     case HAL_NRF_PIPE5:
00364       en_rxaddr.value = en_rxaddr.value & (uint8_t)~SET_BIT(pipe_num);
00365       en_aa.value = en_aa.value & (uint8_t)~SET_BIT(pipe_num);
00366       break;
00367 
00368     case HAL_NRF_ALL:
00369       en_rxaddr.value = 0U;
00370       en_aa.value = 0U;
00371       break;
00372 
00373     case HAL_NRF_TX:
00374     default:
00375       break;
00376   }
00377 
00378   hal_nrf_write_reg (EN_RXADDR, en_rxaddr.value);
00379   hal_nrf_write_reg (EN_AA, en_aa.value);
00380 }
00381 
00382 void hal_nrf_set_address(const hal_nrf_address_t address, const uint8_t *addr)
00383 {
00384   switch(address)
00385   {
00386     case HAL_NRF_TX:
00387     case HAL_NRF_PIPE0:
00388     case HAL_NRF_PIPE1:
00389       hal_nrf_write_multibyte_reg(W_REGISTER + RX_ADDR_P0 + (uint8_t) address, addr, hal_nrf_get_address_width());
00390       break;
00391     case HAL_NRF_PIPE2:
00392     case HAL_NRF_PIPE3:
00393     case HAL_NRF_PIPE4:
00394     case HAL_NRF_PIPE5:
00395       hal_nrf_write_reg (RX_ADDR_P0 + (uint8_t) address, *addr);
00396       break;
00397 
00398     case HAL_NRF_ALL:
00399     default:
00400       break;
00401   }
00402 }
00403 
00404 uint8_t hal_nrf_get_address(uint8_t address, uint8_t *addr)
00405 {
00406   switch (address)
00407   {
00408     case HAL_NRF_PIPE0:
00409     case HAL_NRF_PIPE1:
00410     case HAL_NRF_TX:
00411       return (uint8_t)hal_nrf_read_multibyte_reg (address, addr);
00412     default:
00413       *addr = hal_nrf_read_reg(RX_ADDR_P0 + address);
00414       return 1U;
00415   }
00416 }
00417 
00418 void hal_nrf_set_auto_retr(uint8_t retr, uint16_t delay)
00419 {
00420   setup_retr_t setup_retr;
00421   setup_retr.bits.ard = (uint8_t)(delay >> 8);
00422   setup_retr.bits.arc = retr;
00423 
00424   hal_nrf_write_reg (SETUP_RETR, setup_retr.value);
00425 }
00426 
00427 void hal_nrf_set_address_width(hal_nrf_address_width_t address_width)
00428 {
00429   setup_aw_t setup_aw;
00430   setup_aw.value = 0U;
00431   setup_aw.bits.aw = (uint8_t)address_width - 2U;
00432 
00433   hal_nrf_write_reg (SETUP_AW, setup_aw.value);
00434 }
00435 
00436 uint8_t hal_nrf_get_address_width (void)
00437 {
00438   return hal_nrf_read_reg (SETUP_AW) + 2U;
00439 }
00440 
00441 void hal_nrf_set_rx_payload_width(uint8_t pipe_num, uint8_t pload_width)
00442 {
00443   hal_nrf_write_reg (RX_PW_P0 + pipe_num, pload_width);
00444 }
00445 
00446 uint8_t hal_nrf_get_pipe_status(uint8_t pipe_num)
00447 {
00448   en_pipes_t en_rxaddr;
00449   en_pipes_t en_aa;
00450   uint8_t en_rx_r, en_aa_r;
00451 
00452   en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
00453   en_aa.value = hal_nrf_read_reg (EN_AA);
00454 
00455   switch (pipe_num)
00456   {
00457     case 0:
00458       en_rx_r = en_rxaddr.bits.pipe_0;
00459       en_aa_r = en_aa.bits.pipe_0;
00460       break;
00461     case 1:
00462       en_rx_r = en_rxaddr.bits.pipe_1;
00463       en_aa_r = en_aa.bits.pipe_1;
00464       break;
00465     case 2:
00466       en_rx_r = en_rxaddr.bits.pipe_2;
00467       en_aa_r = en_aa.bits.pipe_2;
00468       break;
00469     case 3:
00470       en_rx_r = en_rxaddr.bits.pipe_3;
00471       en_aa_r = en_aa.bits.pipe_3;
00472       break;
00473     case 4:
00474       en_rx_r = en_rxaddr.bits.pipe_4;
00475       en_aa_r = en_aa.bits.pipe_4;
00476       break;
00477     case 5:
00478       en_rx_r = en_rxaddr.bits.pipe_5;
00479       en_aa_r = en_aa.bits.pipe_5;
00480       break;
00481     default:
00482       en_rx_r = 0U;
00483       en_aa_r = 0U;
00484       break;
00485   }
00486 
00487   return (uint8_t)(en_aa_r << 1) + en_rx_r;
00488 }
00489 
00490 uint8_t hal_nrf_get_auto_retr_status(void)
00491 {
00492   return hal_nrf_read_reg(OBSERVE_TX);
00493 }
00494 
00495 uint8_t hal_nrf_get_packet_lost_ctr(void)
00496 {
00497   return ((hal_nrf_read_reg(OBSERVE_TX) & (BIT_7|BIT_6|BIT_5|BIT_4)) >> 4);
00498 }
00499 
00500 uint8_t hal_nrf_get_rx_payload_width(uint8_t pipe_num)
00501 {
00502   uint8_t pw;
00503 
00504   switch (pipe_num)
00505   {
00506     case 0:
00507       pw = hal_nrf_read_reg (RX_PW_P0);
00508       break;
00509     case 1:
00510       pw = hal_nrf_read_reg (RX_PW_P1);
00511       break;
00512     case 2:
00513       pw = hal_nrf_read_reg (RX_PW_P2);
00514       break;
00515     case 3:
00516       pw = hal_nrf_read_reg (RX_PW_P3);
00517       break;
00518     case 4:
00519       pw = hal_nrf_read_reg (RX_PW_P4);
00520       break;
00521     case 5:
00522       pw = hal_nrf_read_reg (RX_PW_P5);
00523       break;
00524     default:
00525       pw = 0U;
00526       break;
00527   }
00528 
00529   return pw;
00530 }
00531 
00532 void hal_nrf_set_rf_channel(uint8_t channel)
00533 {
00534   rf_ch_t rf_ch;
00535   rf_ch.value = 0U;
00536   rf_ch.bits.rf_ch = channel;
00537   hal_nrf_write_reg (RF_CH, rf_ch.value);
00538 }
00539 
00540 void hal_nrf_set_output_power(hal_nrf_output_power_t power)
00541 {
00542   rf_setup_t rf_setup;
00543   rf_setup.value = hal_nrf_read_reg (RF_SETUP);
00544 
00545   rf_setup.bits.rf_pwr = (uint8_t)power;
00546 
00547   hal_nrf_write_reg (RF_SETUP, rf_setup.value);
00548 }
00549 
00550 void hal_nrf_set_datarate(hal_nrf_datarate_t datarate)
00551 {
00552   rf_setup_t rf_setup;
00553   rf_setup.value = hal_nrf_read_reg (RF_SETUP);
00554 
00555   switch (datarate)
00556   {
00557     case HAL_NRF_250KBPS:
00558       rf_setup.bits.rf_dr_low = 1U;
00559       rf_setup.bits.rf_dr_high = 0U;
00560       break;
00561     case HAL_NRF_1MBPS:
00562       rf_setup.bits.rf_dr_low = 0U;
00563       rf_setup.bits.rf_dr_high = 0U;
00564       break;
00565     case HAL_NRF_2MBPS:
00566     default:
00567       rf_setup.bits.rf_dr_low = 0U;
00568       rf_setup.bits.rf_dr_high = 1U;
00569       break;
00570   }
00571 
00572   hal_nrf_write_reg (RF_SETUP, rf_setup.value);
00573 }
00574 
00575 bool hal_nrf_rx_fifo_empty(void)
00576 {
00577   return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> RX_EMPTY) & 0x01U);
00578 }
00579 
00580 bool hal_nrf_rx_fifo_full(void)
00581 {
00582   return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> RX_FULL) & 0x01U);
00583 }
00584 
00585 bool hal_nrf_tx_fifo_empty(void)
00586 {
00587   return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_EMPTY) & 0x01U);
00588 }
00589 
00590 bool hal_nrf_tx_fifo_full(void)
00591 {
00592   return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_FIFO_FULL) & 0x01U);
00593 }
00594 
00595 uint8_t hal_nrf_get_tx_fifo_status(void)
00596 {
00597   return ((hal_nrf_read_reg(FIFO_STATUS) & ((1U<<TX_FIFO_FULL)|(1U<<TX_EMPTY))) >> 4);
00598 }
00599 
00600 uint8_t hal_nrf_get_rx_fifo_status(void)
00601 {
00602   return (hal_nrf_read_reg(FIFO_STATUS) & ((1U<<RX_FULL)|(1U<<RX_EMPTY)));
00603 }
00604 
00605 uint8_t hal_nrf_get_fifo_status(void)
00606 {
00607   return hal_nrf_read_reg(FIFO_STATUS);
00608 }
00609 
00610 uint8_t hal_nrf_get_transmit_attempts(void)
00611 {
00612   return (hal_nrf_read_reg(OBSERVE_TX) & (BIT_3|BIT_2|BIT_1|BIT_0));
00613 }
00614 
00615 bool hal_nrf_get_carrier_detect(void)
00616 {
00617   return (bool)(hal_nrf_read_reg(CD) & 0x01U);
00618 }
00619 
00620 void hal_nrf_activate_features(void)
00621 {return;}
00622 
00623 void hal_nrf_setup_dynamic_payload (uint8_t setup)
00624 {
00625   en_pipes_t dynpd;
00626   dynpd.value = setup & (uint8_t)~0xC0U;
00627 
00628   hal_nrf_write_reg (DYNPD, dynpd.value);
00629 }
00630 
00631 void hal_nrf_enable_dynamic_payload(bool enable)
00632 {
00633   feature_t feature;
00634   feature.value = hal_nrf_read_reg (FEATURE);
00635   feature.bits.en_dpl = (enable) ? 1U : 0U;
00636 
00637   hal_nrf_write_reg (FEATURE, feature.value);
00638 }
00639 
00640 void hal_nrf_enable_ack_payload(bool enable)
00641 {
00642   feature_t feature;
00643   feature.value = hal_nrf_read_reg (FEATURE);
00644   feature.bits.en_ack_pay = (enable) ? 1U : 0U;
00645 
00646   hal_nrf_write_reg (FEATURE, feature.value);
00647 }
00648 
00649 void hal_nrf_enable_dynamic_ack(bool enable)
00650 {
00651   feature_t feature;
00652   feature.value = hal_nrf_read_reg (FEATURE);
00653   feature.bits.en_dyn_ack = (enable) ? 1U : 0U;
00654 
00655   hal_nrf_write_reg (FEATURE, feature.value);
00656 }
00657 
00658 void hal_nrf_write_tx_payload(const uint8_t *tx_pload, uint8_t length)
00659 {
00660   hal_nrf_write_multibyte_reg(W_TX_PAYLOAD, tx_pload, length);
00661 }
00662 
00663 void hal_nrf_write_tx_payload_noack(const uint8_t *tx_pload, uint8_t length)
00664 {
00665   hal_nrf_write_multibyte_reg(W_TX_PAYLOAD_NOACK, tx_pload, length);
00666 }
00667 
00668 void hal_nrf_write_ack_payload(uint8_t pipe, const uint8_t *tx_pload, uint8_t length)
00669 {
00670   hal_nrf_write_multibyte_reg(W_ACK_PAYLOAD | pipe, tx_pload, length);
00671 }
00672 
00673 uint8_t hal_nrf_read_rx_payload_width(void)
00674 {
00675   return hal_nrf_read_reg(R_RX_PL_WID);
00676 }
00677 
00678 uint16_t hal_nrf_read_rx_payload(uint8_t *rx_pload)
00679 {
00680   return hal_nrf_read_multibyte_reg(UINT8(HAL_NRF_RX_PLOAD), rx_pload);
00681 }
00682 
00683 uint8_t hal_nrf_get_rx_data_source(void)
00684 {
00685   return ((hal_nrf_nop() & (BIT_3|BIT_2|BIT_1)) >> 1);
00686 }
00687 
00688 void hal_nrf_reuse_tx(void)
00689 {
00690   CSN_LOW();
00691   hal_nrf_rw(REUSE_TX_PL);
00692   CSN_HIGH();
00693 }
00694 
00695 bool hal_nrf_get_reuse_tx_status(void)
00696 {
00697   return (bool)((hal_nrf_get_fifo_status() & (1U<<TX_REUSE)) >> TX_REUSE);
00698 }
00699 
00700 void hal_nrf_flush_rx(void)
00701 {
00702   CSN_LOW();
00703   hal_nrf_rw(FLUSH_RX);
00704   CSN_HIGH();
00705 }
00706 
00707 void hal_nrf_flush_tx(void)
00708 {
00709   CSN_LOW();
00710   hal_nrf_rw(FLUSH_TX);
00711   CSN_HIGH();
00712 }
00713 
00714 uint8_t hal_nrf_nop(void)
00715 {
00716   uint8_t retval;
00717 
00718   CSN_LOW();
00719   retval = hal_nrf_rw(NOP);
00720   CSN_HIGH();
00721 
00722   return retval;
00723 }
00724 
00725 void hal_nrf_set_pll_mode(bool pll_lock)
00726 {
00727   rf_setup_t rf_setup;
00728   rf_setup.value = hal_nrf_read_reg (RF_SETUP);
00729   rf_setup.bits.pll_lock = (pll_lock) ? 1U : 0U;
00730 
00731   hal_nrf_write_reg(RF_SETUP, rf_setup.value);
00732 }
00733 
00734 void hal_nrf_enable_continious_wave (bool enable)
00735 {
00736   rf_setup_t rf_setup;
00737   rf_setup.value = hal_nrf_read_reg (RF_SETUP);
00738   rf_setup.bits.cont_wave = (enable ? 1U : 0U);
00739 
00740   hal_nrf_write_reg(RF_SETUP, rf_setup.value);
00741 }
00742 
00743 uint8_t hal_nrf_read_reg(uint8_t reg)
00744 {
00745   uint8_t temp;
00746 
00747   CSN_LOW();
00748 
00749   HAL_NRF_HW_SPI_WRITE(reg);
00750   while(HAL_NRF_HW_SPI_BUSY) {}
00751   temp = HAL_NRF_HW_SPI_READ();
00752 
00753   HAL_NRF_HW_SPI_WRITE(0U);
00754   while(HAL_NRF_HW_SPI_BUSY) {}
00755   temp = HAL_NRF_HW_SPI_READ();
00756 
00757   CSN_HIGH();
00758 
00759   return temp;
00760 }
00761 
00762 uint8_t hal_nrf_write_reg(uint8_t reg, uint8_t value)
00763 {
00764   uint8_t retval;
00765 /*lint -esym(550,dummy) symbol not accessed*/
00766 /*lint -esym(438,dummy) last assigned value not used*/
00767 /*lint -esym(838,dummy) previously assigned value not used*/
00768   uint8_t volatile dummy;
00769 
00770   CSN_LOW();
00771 
00772   HAL_NRF_HW_SPI_WRITE((W_REGISTER + reg));
00773   while(HAL_NRF_HW_SPI_BUSY) {}
00774   retval = HAL_NRF_HW_SPI_READ();
00775 
00776   HAL_NRF_HW_SPI_WRITE(value);
00777   while(HAL_NRF_HW_SPI_BUSY) {}
00778   dummy = HAL_NRF_HW_SPI_READ();
00779 
00780   CSN_HIGH();
00781 
00782   return retval;
00783 }
00784 
00785 #define NRF_READ_MULTIBYTE_REG_COMMON_BODY \
00786     do \
00787     { \
00788       HAL_NRF_HW_SPI_WRITE(0U); \
00789       if (!first_round) \
00790       { \
00791         *buf = read_byte; \
00792         buf++; \
00793       } \
00794       else \
00795       { \
00796         first_round = false; \
00797       } \
00798       /* wait for byte transfer finished */ \
00799       while(HAL_NRF_HW_SPI_BUSY){} \
00800       read_byte = HAL_NRF_HW_SPI_READ(); \
00801     } while (--ctr); \
00802     *buf = read_byte;
00803 
00804 uint16_t hal_nrf_read_multibyte_reg(uint8_t reg, uint8_t *pbuf)
00805 {
00806   uint8_t ctr, length;
00807   uint8_t memtype;
00808   uint8_t read_byte; /*lint -esym(530,read_byte) symbol not initialized*/
00809   bool first_round;
00810   first_round = true;
00811 
00812   memtype = *(uint8_t*)(&pbuf);
00813 
00814   switch(reg)
00815   {
00816     case HAL_NRF_PIPE0:
00817     case HAL_NRF_PIPE1:
00818     case HAL_NRF_TX:
00819       length = ctr = hal_nrf_get_address_width();
00820       CSN_LOW();
00821       hal_nrf_rw(RX_ADDR_P0 + reg);
00822       break;
00823 
00824     case HAL_NRF_RX_PLOAD:
00825       reg = hal_nrf_get_rx_data_source();
00826       if (reg < 7U)
00827       {
00828         length = ctr = hal_nrf_read_rx_payload_width();
00829         CSN_LOW();
00830         hal_nrf_rw(R_RX_PAYLOAD);
00831       }
00832       else
00833       {
00834         ctr = length = 0U;
00835       }
00836       break;
00837 
00838     default:
00839       ctr = length = 0U;
00840       break;
00841   }
00842 
00843   if (memtype == 0x00U)
00844   {
00845     uint8_t data *buf = (uint8_t data *)pbuf;
00846     NRF_READ_MULTIBYTE_REG_COMMON_BODY
00847   }
00848   else if (memtype == 0x01U)
00849   {
00850     uint8_t xdata *buf = (uint8_t xdata *)pbuf;
00851     NRF_READ_MULTIBYTE_REG_COMMON_BODY
00852   }
00853   else if (memtype == 0xFEU)
00854   {
00855     uint8_t pdata *buf = (uint8_t pdata *)pbuf;
00856     NRF_READ_MULTIBYTE_REG_COMMON_BODY
00857   }
00858   else
00859   {
00860     uint8_t *buf = (uint8_t *)pbuf;
00861     NRF_READ_MULTIBYTE_REG_COMMON_BODY
00862   }
00863 
00864   CSN_HIGH();
00865 
00866   return (((uint16_t) reg << 8) | length);
00867 }
00868 
00869 #define NRF_WRITE_MULTIBYTE_REG_COMMON_BODY \
00870   do \
00871   { \
00872     next = *buf; \
00873     buf++; \
00874     while(HAL_NRF_HW_SPI_BUSY) {}  /* wait for byte transfer finished */ \
00875     dummy = HAL_NRF_HW_SPI_READ(); \
00876     HAL_NRF_HW_SPI_WRITE(next); \
00877   } while (--length);
00878 /*lint -esym(550,dummy) symbol not accessed*/ \
00879 /*lint -esym(438,dummy) last assigned value not used*/ \
00880 /*lint -esym(838,dummy) previously assigned value not used*/ \
00881 void hal_nrf_write_multibyte_reg(uint8_t reg, const uint8_t *pbuf, uint8_t length)
00882 {
00883   uint8_t memtype;
00884   uint8_t next;
00885   uint8_t volatile dummy;
00886 
00887   memtype = *(uint8_t*)(&pbuf);
00888 
00889   CSN_LOW();
00890   HAL_NRF_HW_SPI_WRITE(reg);
00891 
00892   if (memtype == 0x00U)
00893   {
00894     const uint8_t data *buf = (const uint8_t data *)pbuf;
00895     NRF_WRITE_MULTIBYTE_REG_COMMON_BODY
00896   }
00897   else if (memtype == 0x01U)
00898   {
00899     const uint8_t xdata *buf = (const uint8_t xdata *)pbuf;
00900     NRF_WRITE_MULTIBYTE_REG_COMMON_BODY
00901   }
00902   else if (memtype == 0xFEU)
00903   {
00904     const uint8_t pdata *buf = (const uint8_t pdata *)pbuf;
00905     NRF_WRITE_MULTIBYTE_REG_COMMON_BODY
00906   }
00907   else
00908   {
00909     const uint8_t *buf = (const uint8_t *)pbuf;
00910     NRF_WRITE_MULTIBYTE_REG_COMMON_BODY
00911   }
00912 
00913   while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
00914   dummy = HAL_NRF_HW_SPI_READ();
00915   CSN_HIGH();
00916 }

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