Register definitions for nRF24L01+. More...
Go to the source code of this file.
Defines | |
- Instruction Set - | |
| #define | W_REGISTER 0x20U |
| #define | R_RX_PAYLOAD 0x61U |
| #define | W_TX_PAYLOAD 0xA0U |
| #define | FLUSH_TX 0xE1U |
| #define | FLUSH_RX 0xE2U |
| #define | REUSE_TX_PL 0xE3U |
| #define | ACTIVATE 0x50U |
| #define | R_RX_PL_WID 0x60U |
| #define | W_ACK_PAYLOAD 0xA8U |
| #define | W_TX_PAYLOAD_NOACK 0xB0U |
| #define | NOP 0xFFU |
- Register Memory Map - | |
| #define | CONFIG 0x00U |
| #define | EN_AA 0x01U |
| #define | EN_RXADDR 0x02U |
| #define | SETUP_AW 0x03U |
| #define | SETUP_RETR 0x04U |
| #define | RF_CH 0x05U |
| #define | RF_SETUP 0x06U |
| #define | STATUS 0x07U |
| #define | OBSERVE_TX 0x08U |
| #define | CD 0x09U |
| #define | RX_ADDR_P0 0x0AU |
| #define | RX_ADDR_P1 0x0BU |
| #define | RX_ADDR_P2 0x0CU |
| #define | RX_ADDR_P3 0x0DU |
| #define | RX_ADDR_P4 0x0EU |
| #define | RX_ADDR_P5 0x0FU |
| #define | TX_ADDR 0x10U |
| #define | RX_PW_P0 0x11U |
| #define | RX_PW_P1 0x12U |
| #define | RX_PW_P2 0x13U |
| #define | RX_PW_P3 0x14U |
| #define | RX_PW_P4 0x15U |
| #define | RX_PW_P5 0x16U |
| #define | FIFO_STATUS 0x17U |
| #define | DYNPD 0x1CU |
| #define | FEATURE 0x1DU |
CONFIG register bit definitions | |
| #define | MASK_RX_DR 6 |
| #define | MASK_TX_DS 5 |
| #define | MASK_MAX_RT 4 |
| #define | EN_CRC 3 |
| #define | CRCO 2 |
| #define | PWR_UP 1 |
| #define | PRIM_RX 0 |
RF_SETUP register bit definitions | |
| #define | PLL_LOCK 4 |
| #define | RF_DR 3 |
| #define | RF_PWR1 2 |
| #define | RF_PWR0 1 |
| #define | LNA_HCURR 0 |
STATUS register bit definitions | |
| #define | RX_DR 6 |
| #define | TX_DS 5 |
| #define | MAX_RT 4 |
| #define | TX_FULL 0 |
FIFO_STATUS register bit definitions | |
| #define | TX_REUSE 6 |
| #define | TX_FIFO_FULL 5 |
| #define | TX_EMPTY 4 |
| #define | RX_FULL 1 |
| #define | RX_EMPTY 0 |
Enumerations | |
| enum | hal_nrf_irq_source_t { HAL_NRF_MAX_RT = 4, HAL_NRF_TX_DS, HAL_NRF_RX_DR } |
| enum | hal_nrf_operation_mode_t { HAL_NRF_PTX, HAL_NRF_PRX } |
| enum | hal_nrf_pwr_mode_t { HAL_NRF_PWR_DOWN, HAL_NRF_PWR_UP } |
| enum | hal_nrf_output_power_t { HAL_NRF_18DBM, HAL_NRF_12DBM, HAL_NRF_6DBM, HAL_NRF_0DBM } |
| enum | hal_nrf_datarate_t { HAL_NRF_1MBPS, HAL_NRF_2MBPS, HAL_NRF_250KBPS } |
| enum | hal_nrf_crc_mode_t { HAL_NRF_CRC_OFF, HAL_NRF_CRC_8BIT, HAL_NRF_CRC_16BIT } |
| enum | hal_nrf_pload_command_t { HAL_NRF_TX_PLOAD = 7, HAL_NRF_RX_PLOAD, HAL_NRF_ACK_PLOAD } |
| enum | hal_nrf_address_t { HAL_NRF_PIPE0 = 0, HAL_NRF_PIPE1, HAL_NRF_PIPE2, HAL_NRF_PIPE3, HAL_NRF_PIPE4, HAL_NRF_PIPE5, HAL_NRF_TX, HAL_NRF_ALL = 0xFF } |
| enum | hal_nrf_address_width_t { HAL_NRF_AW_3BYTES = 3, HAL_NRF_AW_4BYTES, HAL_NRF_AW_5BYTES } |
Register definitions for nRF24L01+.
Header file defining register mapping with bit definitions. This file is radio-chip dependent, and are included with the hal_nrf.h
Definition in file hal_nrf_reg.h.
| #define W_REGISTER 0x20U |
Register write command
Definition at line 29 of file hal_nrf_reg.h.
| #define R_RX_PAYLOAD 0x61U |
Read RX payload command
Definition at line 30 of file hal_nrf_reg.h.
| #define W_TX_PAYLOAD 0xA0U |
Write TX payload command
Definition at line 31 of file hal_nrf_reg.h.
| #define FLUSH_TX 0xE1U |
Flush TX register command
Definition at line 32 of file hal_nrf_reg.h.
| #define FLUSH_RX 0xE2U |
Flush RX register command
Definition at line 33 of file hal_nrf_reg.h.
| #define REUSE_TX_PL 0xE3U |
Reuse TX payload command
Definition at line 34 of file hal_nrf_reg.h.
| #define ACTIVATE 0x50U |
Activate features
Definition at line 35 of file hal_nrf_reg.h.
| #define R_RX_PL_WID 0x60U |
Read RX payload command
Definition at line 36 of file hal_nrf_reg.h.
| #define W_ACK_PAYLOAD 0xA8U |
Write ACK payload command
Definition at line 37 of file hal_nrf_reg.h.
| #define W_TX_PAYLOAD_NOACK 0xB0U |
Write ACK payload command
Definition at line 38 of file hal_nrf_reg.h.
| #define NOP 0xFFU |
No Operation command, used for reading status register
Definition at line 39 of file hal_nrf_reg.h.
| #define CONFIG 0x00U |
nRF24L01 config register
Definition at line 45 of file hal_nrf_reg.h.
| #define EN_AA 0x01U |
nRF24L01 enable Auto-Acknowledge register
Definition at line 46 of file hal_nrf_reg.h.
| #define EN_RXADDR 0x02U |
nRF24L01 enable RX addresses register
Definition at line 47 of file hal_nrf_reg.h.
| #define SETUP_AW 0x03U |
nRF24L01 setup of address width register
Definition at line 48 of file hal_nrf_reg.h.
| #define SETUP_RETR 0x04U |
nRF24L01 setup of automatic retransmission register
Definition at line 49 of file hal_nrf_reg.h.
| #define RF_CH 0x05U |
nRF24L01 RF channel register
Definition at line 50 of file hal_nrf_reg.h.
| #define RF_SETUP 0x06U |
nRF24L01 RF setup register
Definition at line 51 of file hal_nrf_reg.h.
| #define STATUS 0x07U |
nRF24L01 status register
Definition at line 52 of file hal_nrf_reg.h.
| #define OBSERVE_TX 0x08U |
nRF24L01 transmit observe register
Definition at line 53 of file hal_nrf_reg.h.
| #define CD 0x09U |
nRF24L01 carrier detect register
Definition at line 54 of file hal_nrf_reg.h.
| #define RX_ADDR_P0 0x0AU |
nRF24L01 receive address data pipe0
Definition at line 55 of file hal_nrf_reg.h.
| #define RX_ADDR_P1 0x0BU |
nRF24L01 receive address data pipe1
Definition at line 56 of file hal_nrf_reg.h.
| #define RX_ADDR_P2 0x0CU |
nRF24L01 receive address data pipe2
Definition at line 57 of file hal_nrf_reg.h.
| #define RX_ADDR_P3 0x0DU |
nRF24L01 receive address data pipe3
Definition at line 58 of file hal_nrf_reg.h.
| #define RX_ADDR_P4 0x0EU |
nRF24L01 receive address data pipe4
Definition at line 59 of file hal_nrf_reg.h.
| #define RX_ADDR_P5 0x0FU |
nRF24L01 receive address data pipe5
Definition at line 60 of file hal_nrf_reg.h.
| #define TX_ADDR 0x10U |
nRF24L01 transmit address
Definition at line 61 of file hal_nrf_reg.h.
| #define RX_PW_P0 0x11U |
nRF24L01 # of bytes in rx payload for pipe0
Definition at line 62 of file hal_nrf_reg.h.
| #define RX_PW_P1 0x12U |
nRF24L01 # of bytes in rx payload for pipe1
Definition at line 63 of file hal_nrf_reg.h.
| #define RX_PW_P2 0x13U |
nRF24L01 # of bytes in rx payload for pipe2
Definition at line 64 of file hal_nrf_reg.h.
| #define RX_PW_P3 0x14U |
nRF24L01 # of bytes in rx payload for pipe3
Definition at line 65 of file hal_nrf_reg.h.
| #define RX_PW_P4 0x15U |
nRF24L01 # of bytes in rx payload for pipe4
Definition at line 66 of file hal_nrf_reg.h.
| #define RX_PW_P5 0x16U |
nRF24L01 # of bytes in rx payload for pipe5
Definition at line 67 of file hal_nrf_reg.h.
| #define FIFO_STATUS 0x17U |
nRF24L01 FIFO status register
Definition at line 68 of file hal_nrf_reg.h.
| #define DYNPD 0x1CU |
nRF24L01 Dynamic payload setup
Definition at line 69 of file hal_nrf_reg.h.
| #define FEATURE 0x1DU |
nRF24L01 Exclusive feature setup
Definition at line 70 of file hal_nrf_reg.h.
| #define MASK_RX_DR 6 |
CONFIG register bit 6
Definition at line 189 of file hal_nrf_reg.h.
| #define MASK_TX_DS 5 |
CONFIG register bit 5
Definition at line 190 of file hal_nrf_reg.h.
| #define MASK_MAX_RT 4 |
CONFIG register bit 4
Definition at line 191 of file hal_nrf_reg.h.
| #define EN_CRC 3 |
CONFIG register bit 3
Definition at line 192 of file hal_nrf_reg.h.
| #define CRCO 2 |
CONFIG register bit 2
Definition at line 193 of file hal_nrf_reg.h.
| #define PWR_UP 1 |
CONFIG register bit 1
Definition at line 194 of file hal_nrf_reg.h.
| #define PRIM_RX 0 |
CONFIG register bit 0
Definition at line 195 of file hal_nrf_reg.h.
| #define PLL_LOCK 4 |
RF_SETUP register bit 4
Definition at line 200 of file hal_nrf_reg.h.
| #define RF_DR 3 |
RF_SETUP register bit 3
Definition at line 201 of file hal_nrf_reg.h.
| #define RF_PWR1 2 |
RF_SETUP register bit 2
Definition at line 202 of file hal_nrf_reg.h.
| #define RF_PWR0 1 |
RF_SETUP register bit 1
Definition at line 203 of file hal_nrf_reg.h.
| #define LNA_HCURR 0 |
RF_SETUP register bit 0
Definition at line 204 of file hal_nrf_reg.h.
| #define RX_DR 6 |
STATUS register bit 6
Definition at line 210 of file hal_nrf_reg.h.
| #define TX_DS 5 |
STATUS register bit 5
Definition at line 211 of file hal_nrf_reg.h.
| #define MAX_RT 4 |
STATUS register bit 4
Definition at line 212 of file hal_nrf_reg.h.
| #define TX_FULL 0 |
STATUS register bit 0
Definition at line 213 of file hal_nrf_reg.h.
| #define TX_REUSE 6 |
FIFO_STATUS register bit 6
Definition at line 219 of file hal_nrf_reg.h.
| #define TX_FIFO_FULL 5 |
FIFO_STATUS register bit 5
Definition at line 220 of file hal_nrf_reg.h.
| #define TX_EMPTY 4 |
FIFO_STATUS register bit 4
Definition at line 221 of file hal_nrf_reg.h.
| #define RX_FULL 1 |
FIFO_STATUS register bit 1
Definition at line 222 of file hal_nrf_reg.h.
| #define RX_EMPTY 0 |
FIFO_STATUS register bit 0
Definition at line 223 of file hal_nrf_reg.h.
| enum hal_nrf_irq_source_t |
An enum describing the radio's irq sources.
| HAL_NRF_MAX_RT |
Max retries interrupt |
| HAL_NRF_TX_DS |
TX data sent interrupt |
| HAL_NRF_RX_DR |
RX data received interrupt |
Definition at line 81 of file hal_nrf_reg.h.
An enum describing the radio's power mode.
Definition at line 91 of file hal_nrf_reg.h.
| enum hal_nrf_pwr_mode_t |
An enum describing the radio's power mode.
Definition at line 99 of file hal_nrf_reg.h.
An enum describing the radio's output power mode's.
| HAL_NRF_18DBM |
Output power set to -18dBm |
| HAL_NRF_12DBM |
Output power set to -12dBm |
| HAL_NRF_6DBM |
Output power set to -6dBm |
| HAL_NRF_0DBM |
Output power set to 0dBm |
Definition at line 107 of file hal_nrf_reg.h.
| enum hal_nrf_datarate_t |
An enum describing the radio's on-air datarate.
| HAL_NRF_1MBPS |
Datarate set to 1 Mbps |
| HAL_NRF_2MBPS |
Datarate set to 2 Mbps |
| HAL_NRF_250KBPS |
Datarate set to 250 kbps |
Definition at line 117 of file hal_nrf_reg.h.
| enum hal_nrf_crc_mode_t |
An enum describing the radio's CRC mode.
| HAL_NRF_CRC_OFF |
CRC check disabled |
| HAL_NRF_CRC_8BIT |
CRC check set to 8-bit |
| HAL_NRF_CRC_16BIT |
CRC check set to 16-bit |
Definition at line 126 of file hal_nrf_reg.h.
An enum describing the read/write payload command.
| HAL_NRF_TX_PLOAD |
TX payload definition |
| HAL_NRF_RX_PLOAD |
RX payload definition |
| HAL_NRF_ACK_PLOAD |
Definition at line 135 of file hal_nrf_reg.h.
| enum hal_nrf_address_t |
Structure containing the radio's address map. Pipe0 contains 5 unique address bytes, while pipe[1..5] share the 4 MSB bytes, set in pipe1.
- Remember that the LSB byte for all pipes have to be unique! - An enum describing the nRF24L01 pipe addresses and TX address.
Definition at line 163 of file hal_nrf_reg.h.
{
HAL_NRF_PIPE0 = 0,
HAL_NRF_PIPE1,
HAL_NRF_PIPE2,
HAL_NRF_PIPE3,
HAL_NRF_PIPE4,
HAL_NRF_PIPE5,
HAL_NRF_TX,
HAL_NRF_ALL = 0xFF
} hal_nrf_address_t;
An enum describing the radio's address width.
| HAL_NRF_AW_3BYTES |
Set address width to 3 bytes |
| HAL_NRF_AW_4BYTES |
Set address width to 4 bytes |
| HAL_NRF_AW_5BYTES |
Set address width to 5 bytes |
Definition at line 179 of file hal_nrf_reg.h.
1.7.2