hal/nrf24l01p/hal_nrf_reg.h

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/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
 *
 * The information contained herein is confidential property of Nordic
 * Semiconductor ASA.Terms and conditions of usage are described in detail
 * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
 *
 * Licensees are granted free, non-transferable use of the information. NO
 * WARRENTY of ANY KIND is provided. This heading must NOT be removed from
 * the file.
 *
 * $LastChangedRevision: 2519 $
 */

#ifndef HAL_NRF_REG_H__
#define HAL_NRF_REG_H__

/* nRF24L01 Instruction Definitions */
#define W_REGISTER         0x20U  
#define R_RX_PAYLOAD       0x61U  
#define W_TX_PAYLOAD       0xA0U  
#define FLUSH_TX           0xE1U  
#define FLUSH_RX           0xE2U  
#define REUSE_TX_PL        0xE3U  
#define ACTIVATE           0x50U  
#define R_RX_PL_WID        0x60U  
#define W_ACK_PAYLOAD      0xA8U  
#define W_TX_PAYLOAD_NOACK 0xB0U  
#define NOP                0xFFU  


/* nRF24L01 * Register Definitions * */
#define CONFIG        0x00U  
#define EN_AA         0x01U  
#define EN_RXADDR     0x02U  
#define SETUP_AW      0x03U  
#define SETUP_RETR    0x04U  
#define RF_CH         0x05U  
#define RF_SETUP      0x06U  
#define STATUS        0x07U  
#define OBSERVE_TX    0x08U  
#define CD            0x09U  
#define RX_ADDR_P0    0x0AU  
#define RX_ADDR_P1    0x0BU  
#define RX_ADDR_P2    0x0CU  
#define RX_ADDR_P3    0x0DU  
#define RX_ADDR_P4    0x0EU  
#define RX_ADDR_P5    0x0FU  
#define TX_ADDR       0x10U  
#define RX_PW_P0      0x11U  
#define RX_PW_P1      0x12U  
#define RX_PW_P2      0x13U  
#define RX_PW_P3      0x14U  
#define RX_PW_P4      0x15U  
#define RX_PW_P5      0x16U  
#define FIFO_STATUS   0x17U  
#define DYNPD         0x1CU  
#define FEATURE       0x1DU  

/* nRF24L01 related definitions */
/* Interrupt definitions */
/* Operation mode definitions */

typedef enum {
    HAL_NRF_MAX_RT = 4,     
    HAL_NRF_TX_DS,          
    HAL_NRF_RX_DR           
} hal_nrf_irq_source_t;

/* Operation mode definitions */
typedef enum {
    HAL_NRF_PTX,            
    HAL_NRF_PRX             
} hal_nrf_operation_mode_t;

typedef enum {
    HAL_NRF_PWR_DOWN,       
    HAL_NRF_PWR_UP          
} hal_nrf_pwr_mode_t;

typedef enum {
    HAL_NRF_18DBM,          
    HAL_NRF_12DBM,          
    HAL_NRF_6DBM,           
    HAL_NRF_0DBM            
} hal_nrf_output_power_t;

typedef enum {
    HAL_NRF_1MBPS,          
    HAL_NRF_2MBPS,          
    HAL_NRF_250KBPS         
} hal_nrf_datarate_t;

typedef enum {
    HAL_NRF_CRC_OFF,    
    HAL_NRF_CRC_8BIT,   
    HAL_NRF_CRC_16BIT   
} hal_nrf_crc_mode_t;

typedef enum {
    HAL_NRF_TX_PLOAD = 7,   
    HAL_NRF_RX_PLOAD,        
    HAL_NRF_ACK_PLOAD
} hal_nrf_pload_command_t;

// nRF24L01 Address struct


//typedef struct {
//   uint8_t p0[5];            /**< Pipe0 address, 5 bytes */
//    uint8_t p1[5];            /**< Pipe1 address, 5 bytes, 4 MSB bytes shared for pipe1 to pipe5 */
//    uint8_t p2[1];            /**< Pipe2 address, 1 byte */
//    uint8_t p3[1];            /**< Pipe3 address, 1 byte */
//   uint8_t p4[1];            /**< Pipe3 address, 1 byte */
//   uint8_t p5[1];            /**< Pipe3 address, 1 byte */
//   uint8_t tx[5];            /**< TX address, 5 byte */
//} hal_nrf_l01_addr_map;


typedef enum {
    HAL_NRF_PIPE0 = 0,          
    HAL_NRF_PIPE1,              
    HAL_NRF_PIPE2,              
    HAL_NRF_PIPE3,              
    HAL_NRF_PIPE4,              
    HAL_NRF_PIPE5,              
    HAL_NRF_TX,                 
    HAL_NRF_ALL = 0xFF          
} hal_nrf_address_t;

typedef enum {
    HAL_NRF_AW_3BYTES = 3,      
    HAL_NRF_AW_4BYTES,          
    HAL_NRF_AW_5BYTES           
} hal_nrf_address_width_t;



#define MASK_RX_DR    6     
#define MASK_TX_DS    5     
#define MASK_MAX_RT   4     
#define EN_CRC        3     
#define CRCO          2     
#define PWR_UP        1     
#define PRIM_RX       0     


#define PLL_LOCK      4     
#define RF_DR         3     
#define RF_PWR1       2     
#define RF_PWR0       1     
#define LNA_HCURR     0     

/* STATUS 0x07 */
#define RX_DR         6     
#define TX_DS         5     
#define MAX_RT        4     
#define TX_FULL       0     

/* FIFO_STATUS 0x17 */
#define TX_REUSE      6     
#define TX_FIFO_FULL  5     
#define TX_EMPTY      4     
#define RX_FULL       1     
#define RX_EMPTY      0     

#endif // HAL_NRF_REG_H__