00001 /*-------------------------------------------------------------------------- 00002 * reg24le1.h 00003 * 00004 * Keil C51 header file for the Nordic Semiconductor nRF24LE1 2.4GHz RF 00005 * transceiver with embedded 8051 compatible microcontroller. 00006 * 00007 * 00008 *------------------------------------------------------------------------*/ 00009 #ifndef REG24LE1_H__ 00010 #define REG24LE1_H__ 00011 00012 //----------------------------------------------------------------------------- 00013 // Byte Registers 00014 //----------------------------------------------------------------------------- 00015 00016 sfr P0 = 0x80; 00017 sfr SP = 0x81; 00018 sfr DPL = 0x82; 00019 sfr DPH = 0x83; 00020 sfr DPL1 = 0x84; 00021 sfr DPH1 = 0x85; 00022 sfr PCON = 0x87; 00023 sfr TCON = 0x88; 00024 sfr TMOD = 0x89; 00025 sfr TL0 = 0x8A; 00026 sfr TL1 = 0x8B; 00027 sfr TH0 = 0x8C; 00028 sfr TH1 = 0x8D; 00029 sfr P3CON = 0x8F; 00030 sfr P1 = 0x90; 00031 sfr DPS = 0x92; 00032 sfr P0DIR = 0x93; 00033 sfr P1DIR = 0x94; 00034 sfr P2DIR = 0x95; 00035 sfr P3DIR = 0x96; 00036 sfr P2CON = 0x97; 00037 sfr S0CON = 0x98; 00038 sfr S0BUF = 0x99; 00039 sfr P0CON = 0x9E; 00040 sfr P1CON = 0x9F; 00041 sfr P2 = 0xA0; 00042 sfr PWMDC0 = 0xA1; 00043 sfr PWMDC1 = 0xA2; 00044 sfr CLKCTRL = 0xA3; 00045 sfr PWRDWN = 0xA4; 00046 sfr WUCON = 0xA5; 00047 sfr INTEXP = 0xA6; 00048 sfr MEMCON = 0xA7; 00049 sfr IEN0 = 0xA8; 00050 sfr IP0 = 0xA9; 00051 sfr S0RELL = 0xAA; 00052 sfr RTC2CPT01 = 0xAB; 00053 sfr RTC2CPT10 = 0xAC; 00054 sfr CLKLFCTRL = 0xAD; 00055 sfr OPMCON = 0xAE; 00056 sfr WDSV = 0xAF; 00057 sfr P3 = 0xB0; 00058 sfr RSTREAS = 0xB1; 00059 sfr PWMCON = 0xB2; 00060 sfr RTC2CON = 0xB3; 00061 sfr RTC2CMP0 = 0xB4; 00062 sfr RTC2CMP1 = 0xB5; 00063 sfr RTC2CPT00 = 0xB6; 00064 sfr SPISRDSZ = 0xB7; 00065 sfr IEN1 = 0xB8; 00066 sfr IP1 = 0xB9; 00067 sfr S0RELH = 0xBA; 00068 sfr SPISCON0 = 0xBC; 00069 sfr SPISCON1 = 0xBD; 00070 sfr SPISSTAT = 0xBE; 00071 sfr SPISDAT = 0xBF; 00072 sfr IRCON = 0xC0; 00073 sfr CCEN = 0xC1; 00074 sfr CCL1 = 0xC2; 00075 sfr CCH1 = 0xC3; 00076 sfr CCL2 = 0xC4; 00077 sfr CCH2 = 0xC5; 00078 sfr CCL3 = 0xC6; 00079 sfr CCH3 = 0xC7; 00080 sfr T2CON = 0xC8; 00081 sfr MPAGE = 0xC9; 00082 sfr CRCL = 0xCA; 00083 sfr CRCH = 0xCB; 00084 sfr TL2 = 0xCC; 00085 sfr TH2 = 0xCD; 00086 sfr WUOPC1 = 0xCE; 00087 sfr WUOPC0 = 0xCF; 00088 sfr PSW = 0xD0; 00089 sfr ADCCON3 = 0xD1; 00090 sfr ADCCON2 = 0xD2; 00091 sfr ADCCON1 = 0xD3; 00092 sfr ADCDATH = 0xD4; 00093 sfr ADCDATL = 0xD5; 00094 sfr RNGCTL = 0xD6; 00095 sfr RNGDAT = 0xD7; 00096 sfr ADCON = 0xD8; 00097 sfr W2SADR = 0xD9; 00098 sfr W2DAT = 0xDA; 00099 sfr COMPCON = 0xDB; 00100 sfr POFCON = 0xDC; 00101 sfr CCPDATIA = 0xDD; 00102 sfr CCPDATIB = 0xDE; 00103 sfr CCPDATO = 0xDF; 00104 sfr ACC = 0xE0; 00105 sfr W2CON1 = 0xE1; 00106 sfr W2CON0 = 0xE2; 00107 sfr SPIRCON0 = 0xE4; 00108 sfr SPIRCON1 = 0xE5; 00109 sfr SPIRSTAT = 0xE6; 00110 sfr SPIRDAT = 0xE7; 00111 sfr RFCON = 0xE8; 00112 sfr MD0 = 0xE9; 00113 sfr MD1 = 0xEA; 00114 sfr MD2 = 0xEB; 00115 sfr MD3 = 0xEC; 00116 sfr MD4 = 0xED; 00117 sfr MD5 = 0xEE; 00118 sfr ARCON = 0xEF; 00119 sfr B = 0xF0; 00120 sfr FSR = 0xF8; 00121 sfr FPCR = 0xF9; 00122 sfr FCR = 0xFA; 00123 sfr FDCR = 0xFB; 00124 sfr SPIMCON0 = 0xFC; 00125 sfr SPIMCON1 = 0xFD; 00126 sfr SPIMSTAT = 0xFE; 00127 sfr SPIMDAT = 0xFF; 00128 00129 sfr16 CC1 = 0xC2; 00130 sfr16 CC2 = 0xC4; 00131 sfr16 CC3 = 0xC6; 00132 sfr16 CRC = 0xCA; 00133 sfr16 T2 = 0xCC; 00134 00135 /* FSR */ 00136 sbit MCDIS = FSR^7; 00137 sbit STP = FSR^6; 00138 sbit WEN = FSR^5; 00139 sbit RDYN = FSR^4; 00140 sbit INFEN = FSR^3; 00141 sbit RDIS = FSR^2; 00142 sbit RDEND = FSR^1; 00143 sbit WPEN = FSR^0; 00144 00145 /* PSW */ 00146 sbit CY = PSW^7; 00147 sbit AC = PSW^6; 00148 sbit F0 = PSW^5; 00149 sbit RS1 = PSW^4; 00150 sbit RS0 = PSW^3; 00151 sbit OV = PSW^2; 00152 sbit P = PSW^0; 00153 00154 /* TCON */ 00155 sbit TF1 = TCON^7; 00156 sbit TR1 = TCON^6; 00157 sbit TF0 = TCON^5; 00158 sbit TR0 = TCON^4; 00159 sbit IE1 = TCON^3; 00160 sbit IT1 = TCON^2; 00161 sbit IE0 = TCON^1; 00162 sbit IT0 = TCON^0; 00163 00164 /* S0CON */ 00165 sbit SM0 = S0CON^7; 00166 sbit SM1 = S0CON^6; 00167 sbit SM20 = S0CON^5; 00168 sbit REN0 = S0CON^4; 00169 sbit TB80 = S0CON^3; 00170 sbit RB80 = S0CON^2; 00171 sbit TI0 = S0CON^1; 00172 sbit RI0 = S0CON^0; 00173 00174 /* T2CON */ 00175 sbit T2PS = T2CON^7; 00176 sbit I3FR = T2CON^6; 00177 sbit I2FR = T2CON^5; 00178 sbit T2R1 = T2CON^4; 00179 sbit T2R0 = T2CON^3; 00180 sbit T2CM = T2CON^2; 00181 sbit T2I1 = T2CON^1; 00182 sbit T2I0 = T2CON^0; 00183 00184 /* IEN0 */ 00185 sbit EA = IEN0^7; 00186 sbit ET2 = IEN0^5; 00187 sbit ES0 = IEN0^4; 00188 sbit ET1 = IEN0^3; 00189 sbit EX1 = IEN0^2; 00190 sbit ET0 = IEN0^1; 00191 sbit EX0 = IEN0^0; 00192 00193 /* IEN1 */ 00194 sbit EXEN2 = IEN1^7; 00195 sbit WUIRQ = IEN1^5; 00196 sbit MISC = IEN1^4; 00197 sbit WUPIN = IEN1^3; 00198 sbit SPI = IEN1^2; 00199 sbit RF = IEN1^1; 00200 sbit RFSPI = IEN1^0; 00201 00202 /* IRCON */ 00203 sbit EXF2 = IRCON^7; 00204 sbit TF2 = IRCON^6; 00205 sbit WUF = IRCON^5; 00206 sbit MISCF = IRCON^4; 00207 sbit WUPINF = IRCON^3; 00208 sbit SPIF = IRCON^2; 00209 sbit RFF = IRCON^1; 00210 sbit RFSPIF = IRCON^0; 00211 00212 /* PORT0 */ 00213 sbit P00 = P0^0; 00214 sbit P01 = P0^1; 00215 sbit P02 = P0^2; 00216 sbit P03 = P0^3; 00217 sbit P04 = P0^4; 00218 sbit P05 = P0^5; 00219 sbit P06 = P0^6; 00220 sbit P07 = P0^7; 00221 00222 /* PORT1 */ 00223 sbit P10 = P1^0; 00224 sbit P11 = P1^1; 00225 sbit P12 = P1^2; 00226 sbit P13 = P1^3; 00227 sbit P14 = P1^4; 00228 sbit P15 = P1^5; 00229 sbit P16 = P1^6; 00230 sbit P17 = P1^7; 00231 00232 /* PORT2 */ 00233 sbit P20 = P2^0; 00234 sbit P21 = P2^1; 00235 sbit P22 = P2^2; 00236 sbit P23 = P2^3; 00237 sbit P24 = P2^4; 00238 sbit P25 = P2^5; 00239 sbit P26 = P2^6; 00240 sbit P27 = P2^7; 00241 00242 /* PORT3 */ 00243 sbit P30 = P3^0; 00244 sbit P31 = P3^1; 00245 sbit P32 = P3^2; 00246 sbit P33 = P3^3; 00247 sbit P34 = P3^4; 00248 sbit P35 = P3^5; 00249 sbit P36 = P3^6; 00250 sbit P37 = P3^7; 00251 00252 /* RFCON */ 00253 sbit RFCE = RFCON^0; 00254 sbit RFCSN = RFCON^1; 00255 sbit RFCKEN = RFCON^2; 00256 00257 /* ADCON */ 00258 sbit BD = ADCON^7; 00259 00260 //----------------------------------------------------------------------------- 00261 // Interrupt Vector Definitions 00262 //----------------------------------------------------------------------------- 00263 00264 #define INTERRUPT_IPF 0 // Interrupt from pin 00265 #define INTERRUPT_T0 1 // Timer0 Overflow 00266 #define INTERRUPT_POFIRQ 2 // Power failure interrupt 00267 #define INTERRUPT_T1 3 // Timer1 Overflow 00268 #define INTERRUPT_UART0 4 // UART0, Receive & Transmitt interrupt 00269 #define INTERRUPT_T2 5 // Timer2 Overflow / external reload 00270 #define INTERRUPT_RFRDY 8 // RF SPI ready interrupt 00271 #define INTERRUPT_RFIRQ 9 // RF interrupt 00272 #define INTERRUPT_SERIAL 10 // SPI or 2-wire interrupt 00273 #define INTERRUPT_WUOPIRQ 11 // Wakeup on pin interrupt 00274 #define INTERRUPT_MISCIRQ 12 // Misc interrupt 00275 #define INTERRUPT_TICK 13 // Internal Wakeup 00276 00277 #endif
1.7.2