Go to the source code of this file.
Defines | |
| #define | INTERRUPT_IPF 0 |
| #define | INTERRUPT_T0 1 |
| #define | INTERRUPT_POFIRQ 2 |
| #define | INTERRUPT_T1 3 |
| #define | INTERRUPT_UART0 4 |
| #define | INTERRUPT_T2 5 |
| #define | INTERRUPT_RFRDY 8 |
| #define | INTERRUPT_RFIRQ 9 |
| #define | INTERRUPT_SERIAL 10 |
| #define | INTERRUPT_WUOPIRQ 11 |
| #define | INTERRUPT_MISCIRQ 12 |
| #define | INTERRUPT_TICK 13 |
Variables | |
| sfr | P0 = 0x80 |
| sfr | SP = 0x81 |
| sfr | DPL = 0x82 |
| sfr | DPH = 0x83 |
| sfr | DPL1 = 0x84 |
| sfr | DPH1 = 0x85 |
| sfr | PCON = 0x87 |
| sfr | TCON = 0x88 |
| sfr | TMOD = 0x89 |
| sfr | TL0 = 0x8A |
| sfr | TL1 = 0x8B |
| sfr | TH0 = 0x8C |
| sfr | TH1 = 0x8D |
| sfr | P3CON = 0x8F |
| sfr | P1 = 0x90 |
| sfr | DPS = 0x92 |
| sfr | P0DIR = 0x93 |
| sfr | P1DIR = 0x94 |
| sfr | P2DIR = 0x95 |
| sfr | P3DIR = 0x96 |
| sfr | P2CON = 0x97 |
| sfr | S0CON = 0x98 |
| sfr | S0BUF = 0x99 |
| sfr | P0CON = 0x9E |
| sfr | P1CON = 0x9F |
| sfr | P2 = 0xA0 |
| sfr | PWMDC0 = 0xA1 |
| sfr | PWMDC1 = 0xA2 |
| sfr | CLKCTRL = 0xA3 |
| sfr | PWRDWN = 0xA4 |
| sfr | WUCON = 0xA5 |
| sfr | INTEXP = 0xA6 |
| sfr | MEMCON = 0xA7 |
| sfr | IEN0 = 0xA8 |
| sfr | IP0 = 0xA9 |
| sfr | S0RELL = 0xAA |
| sfr | RTC2CPT01 = 0xAB |
| sfr | RTC2CPT10 = 0xAC |
| sfr | CLKLFCTRL = 0xAD |
| sfr | OPMCON = 0xAE |
| sfr | WDSV = 0xAF |
| sfr | P3 = 0xB0 |
| sfr | RSTREAS = 0xB1 |
| sfr | PWMCON = 0xB2 |
| sfr | RTC2CON = 0xB3 |
| sfr | RTC2CMP0 = 0xB4 |
| sfr | RTC2CMP1 = 0xB5 |
| sfr | RTC2CPT00 = 0xB6 |
| sfr | SPISRDSZ = 0xB7 |
| sfr | IEN1 = 0xB8 |
| sfr | IP1 = 0xB9 |
| sfr | S0RELH = 0xBA |
| sfr | SPISCON0 = 0xBC |
| sfr | SPISCON1 = 0xBD |
| sfr | SPISSTAT = 0xBE |
| sfr | SPISDAT = 0xBF |
| sfr | IRCON = 0xC0 |
| sfr | CCEN = 0xC1 |
| sfr | CCL1 = 0xC2 |
| sfr | CCH1 = 0xC3 |
| sfr | CCL2 = 0xC4 |
| sfr | CCH2 = 0xC5 |
| sfr | CCL3 = 0xC6 |
| sfr | CCH3 = 0xC7 |
| sfr | T2CON = 0xC8 |
| sfr | MPAGE = 0xC9 |
| sfr | CRCL = 0xCA |
| sfr | CRCH = 0xCB |
| sfr | TL2 = 0xCC |
| sfr | TH2 = 0xCD |
| sfr | WUOPC1 = 0xCE |
| sfr | WUOPC0 = 0xCF |
| sfr | PSW = 0xD0 |
| sfr | ADCCON3 = 0xD1 |
| sfr | ADCCON2 = 0xD2 |
| sfr | ADCCON1 = 0xD3 |
| sfr | ADCDATH = 0xD4 |
| sfr | ADCDATL = 0xD5 |
| sfr | RNGCTL = 0xD6 |
| sfr | RNGDAT = 0xD7 |
| sfr | ADCON = 0xD8 |
| sfr | W2SADR = 0xD9 |
| sfr | W2DAT = 0xDA |
| sfr | COMPCON = 0xDB |
| sfr | POFCON = 0xDC |
| sfr | CCPDATIA = 0xDD |
| sfr | CCPDATIB = 0xDE |
| sfr | CCPDATO = 0xDF |
| sfr | ACC = 0xE0 |
| sfr | W2CON1 = 0xE1 |
| sfr | W2CON0 = 0xE2 |
| sfr | SPIRCON0 = 0xE4 |
| sfr | SPIRCON1 = 0xE5 |
| sfr | SPIRSTAT = 0xE6 |
| sfr | SPIRDAT = 0xE7 |
| sfr | RFCON = 0xE8 |
| sfr | MD0 = 0xE9 |
| sfr | MD1 = 0xEA |
| sfr | MD2 = 0xEB |
| sfr | MD3 = 0xEC |
| sfr | MD4 = 0xED |
| sfr | MD5 = 0xEE |
| sfr | ARCON = 0xEF |
| sfr | B = 0xF0 |
| sfr | FSR = 0xF8 |
| sfr | FPCR = 0xF9 |
| sfr | FCR = 0xFA |
| sfr | FDCR = 0xFB |
| sfr | SPIMCON0 = 0xFC |
| sfr | SPIMCON1 = 0xFD |
| sfr | SPIMSTAT = 0xFE |
| sfr | SPIMDAT = 0xFF |
| sfr16 | CC1 = 0xC2 |
| sfr16 | CC2 = 0xC4 |
| sfr16 | CC3 = 0xC6 |
| sfr16 | CRC = 0xCA |
| sfr16 | T2 = 0xCC |
| sbit | MCDIS = FSR^7 |
| sbit | STP = FSR^6 |
| sbit | WEN = FSR^5 |
| sbit | RDYN = FSR^4 |
| sbit | INFEN = FSR^3 |
| sbit | RDIS = FSR^2 |
| sbit | RDEND = FSR^1 |
| sbit | WPEN = FSR^0 |
| sbit | CY = PSW^7 |
| sbit | AC = PSW^6 |
| sbit | F0 = PSW^5 |
| sbit | RS1 = PSW^4 |
| sbit | RS0 = PSW^3 |
| sbit | OV = PSW^2 |
| sbit | P = PSW^0 |
| sbit | TF1 = TCON^7 |
| sbit | TR1 = TCON^6 |
| sbit | TF0 = TCON^5 |
| sbit | TR0 = TCON^4 |
| sbit | IE1 = TCON^3 |
| sbit | IT1 = TCON^2 |
| sbit | IE0 = TCON^1 |
| sbit | IT0 = TCON^0 |
| sbit | SM0 = S0CON^7 |
| sbit | SM1 = S0CON^6 |
| sbit | SM20 = S0CON^5 |
| sbit | REN0 = S0CON^4 |
| sbit | TB80 = S0CON^3 |
| sbit | RB80 = S0CON^2 |
| sbit | TI0 = S0CON^1 |
| sbit | RI0 = S0CON^0 |
| sbit | T2PS = T2CON^7 |
| sbit | I3FR = T2CON^6 |
| sbit | I2FR = T2CON^5 |
| sbit | T2R1 = T2CON^4 |
| sbit | T2R0 = T2CON^3 |
| sbit | T2CM = T2CON^2 |
| sbit | T2I1 = T2CON^1 |
| sbit | T2I0 = T2CON^0 |
| sbit | EA = IEN0^7 |
| sbit | ET2 = IEN0^5 |
| sbit | ES0 = IEN0^4 |
| sbit | ET1 = IEN0^3 |
| sbit | EX1 = IEN0^2 |
| sbit | ET0 = IEN0^1 |
| sbit | EX0 = IEN0^0 |
| sbit | EXEN2 = IEN1^7 |
| sbit | WUIRQ = IEN1^5 |
| sbit | MISC = IEN1^4 |
| sbit | WUPIN = IEN1^3 |
| sbit | SPI = IEN1^2 |
| sbit | RF = IEN1^1 |
| sbit | RFSPI = IEN1^0 |
| sbit | EXF2 = IRCON^7 |
| sbit | TF2 = IRCON^6 |
| sbit | WUF = IRCON^5 |
| sbit | MISCF = IRCON^4 |
| sbit | WUPINF = IRCON^3 |
| sbit | SPIF = IRCON^2 |
| sbit | RFF = IRCON^1 |
| sbit | RFSPIF = IRCON^0 |
| sbit | P00 = P0^0 |
| sbit | P01 = P0^1 |
| sbit | P02 = P0^2 |
| sbit | P03 = P0^3 |
| sbit | P04 = P0^4 |
| sbit | P05 = P0^5 |
| sbit | P06 = P0^6 |
| sbit | P07 = P0^7 |
| sbit | P10 = P1^0 |
| sbit | P11 = P1^1 |
| sbit | P12 = P1^2 |
| sbit | P13 = P1^3 |
| sbit | P14 = P1^4 |
| sbit | P15 = P1^5 |
| sbit | P16 = P1^6 |
| sbit | P17 = P1^7 |
| sbit | P20 = P2^0 |
| sbit | P21 = P2^1 |
| sbit | P22 = P2^2 |
| sbit | P23 = P2^3 |
| sbit | P24 = P2^4 |
| sbit | P25 = P2^5 |
| sbit | P26 = P2^6 |
| sbit | P27 = P2^7 |
| sbit | P30 = P3^0 |
| sbit | P31 = P3^1 |
| sbit | P32 = P3^2 |
| sbit | P33 = P3^3 |
| sbit | P34 = P3^4 |
| sbit | P35 = P3^5 |
| sbit | P36 = P3^6 |
| sbit | P37 = P3^7 |
| sbit | RFCE = RFCON^0 |
| sbit | RFCSN = RFCON^1 |
| sbit | RFCKEN = RFCON^2 |
| sbit | BD = ADCON^7 |
| #define INTERRUPT_IPF 0 |
Definition at line 264 of file reg24le1.h.
| #define INTERRUPT_T0 1 |
Definition at line 265 of file reg24le1.h.
| #define INTERRUPT_POFIRQ 2 |
Definition at line 266 of file reg24le1.h.
| #define INTERRUPT_T1 3 |
Definition at line 267 of file reg24le1.h.
| #define INTERRUPT_UART0 4 |
Definition at line 268 of file reg24le1.h.
| #define INTERRUPT_T2 5 |
Definition at line 269 of file reg24le1.h.
| #define INTERRUPT_RFRDY 8 |
Definition at line 270 of file reg24le1.h.
| #define INTERRUPT_RFIRQ 9 |
Definition at line 271 of file reg24le1.h.
| #define INTERRUPT_SERIAL 10 |
Definition at line 272 of file reg24le1.h.
| #define INTERRUPT_WUOPIRQ 11 |
Definition at line 273 of file reg24le1.h.
| #define INTERRUPT_MISCIRQ 12 |
Definition at line 274 of file reg24le1.h.
| #define INTERRUPT_TICK 13 |
Definition at line 275 of file reg24le1.h.
| sfr P0 = 0x80 |
Definition at line 16 of file reg24le1.h.
| sfr SP = 0x81 |
Definition at line 17 of file reg24le1.h.
| sfr DPL = 0x82 |
Definition at line 18 of file reg24le1.h.
| sfr DPH = 0x83 |
Definition at line 19 of file reg24le1.h.
| sfr DPL1 = 0x84 |
Definition at line 20 of file reg24le1.h.
| sfr DPH1 = 0x85 |
Definition at line 21 of file reg24le1.h.
| sfr PCON = 0x87 |
Definition at line 22 of file reg24le1.h.
| sfr TCON = 0x88 |
Definition at line 23 of file reg24le1.h.
| sfr TMOD = 0x89 |
Definition at line 24 of file reg24le1.h.
| sfr TL0 = 0x8A |
Definition at line 25 of file reg24le1.h.
| sfr TL1 = 0x8B |
Definition at line 26 of file reg24le1.h.
| sfr TH0 = 0x8C |
Definition at line 27 of file reg24le1.h.
| sfr TH1 = 0x8D |
Definition at line 28 of file reg24le1.h.
| sfr P3CON = 0x8F |
Definition at line 29 of file reg24le1.h.
| sfr P1 = 0x90 |
Definition at line 30 of file reg24le1.h.
| sfr DPS = 0x92 |
Definition at line 31 of file reg24le1.h.
| sfr P0DIR = 0x93 |
Definition at line 32 of file reg24le1.h.
| sfr P1DIR = 0x94 |
Definition at line 33 of file reg24le1.h.
| sfr P2DIR = 0x95 |
Definition at line 34 of file reg24le1.h.
| sfr P3DIR = 0x96 |
Definition at line 35 of file reg24le1.h.
| sfr P2CON = 0x97 |
Definition at line 36 of file reg24le1.h.
| sfr S0CON = 0x98 |
Definition at line 37 of file reg24le1.h.
| sfr S0BUF = 0x99 |
Definition at line 38 of file reg24le1.h.
| sfr P0CON = 0x9E |
Definition at line 39 of file reg24le1.h.
| sfr P1CON = 0x9F |
Definition at line 40 of file reg24le1.h.
| sfr P2 = 0xA0 |
Definition at line 41 of file reg24le1.h.
| sfr PWMDC0 = 0xA1 |
Definition at line 42 of file reg24le1.h.
| sfr PWMDC1 = 0xA2 |
Definition at line 43 of file reg24le1.h.
| sfr CLKCTRL = 0xA3 |
Definition at line 44 of file reg24le1.h.
| sfr PWRDWN = 0xA4 |
Definition at line 45 of file reg24le1.h.
| sfr WUCON = 0xA5 |
Definition at line 46 of file reg24le1.h.
| sfr INTEXP = 0xA6 |
Definition at line 47 of file reg24le1.h.
| sfr MEMCON = 0xA7 |
Definition at line 48 of file reg24le1.h.
| sfr IEN0 = 0xA8 |
Definition at line 49 of file reg24le1.h.
| sfr IP0 = 0xA9 |
Definition at line 50 of file reg24le1.h.
| sfr S0RELL = 0xAA |
Definition at line 51 of file reg24le1.h.
| sfr RTC2CPT01 = 0xAB |
Definition at line 52 of file reg24le1.h.
| sfr RTC2CPT10 = 0xAC |
Definition at line 53 of file reg24le1.h.
| sfr CLKLFCTRL = 0xAD |
Definition at line 54 of file reg24le1.h.
| sfr OPMCON = 0xAE |
Definition at line 55 of file reg24le1.h.
| sfr WDSV = 0xAF |
Definition at line 56 of file reg24le1.h.
| sfr P3 = 0xB0 |
Definition at line 57 of file reg24le1.h.
| sfr RSTREAS = 0xB1 |
Definition at line 58 of file reg24le1.h.
| sfr PWMCON = 0xB2 |
Definition at line 59 of file reg24le1.h.
| sfr RTC2CON = 0xB3 |
Definition at line 60 of file reg24le1.h.
| sfr RTC2CMP0 = 0xB4 |
Definition at line 61 of file reg24le1.h.
| sfr RTC2CMP1 = 0xB5 |
Definition at line 62 of file reg24le1.h.
| sfr RTC2CPT00 = 0xB6 |
Definition at line 63 of file reg24le1.h.
| sfr SPISRDSZ = 0xB7 |
Definition at line 64 of file reg24le1.h.
| sfr IEN1 = 0xB8 |
Definition at line 65 of file reg24le1.h.
| sfr IP1 = 0xB9 |
Definition at line 66 of file reg24le1.h.
| sfr S0RELH = 0xBA |
Definition at line 67 of file reg24le1.h.
| sfr SPISCON0 = 0xBC |
Definition at line 68 of file reg24le1.h.
| sfr SPISCON1 = 0xBD |
Definition at line 69 of file reg24le1.h.
| sfr SPISSTAT = 0xBE |
Definition at line 70 of file reg24le1.h.
| sfr SPISDAT = 0xBF |
Definition at line 71 of file reg24le1.h.
| sfr IRCON = 0xC0 |
Definition at line 72 of file reg24le1.h.
| sfr CCEN = 0xC1 |
Definition at line 73 of file reg24le1.h.
| sfr CCL1 = 0xC2 |
Definition at line 74 of file reg24le1.h.
| sfr CCH1 = 0xC3 |
Definition at line 75 of file reg24le1.h.
| sfr CCL2 = 0xC4 |
Definition at line 76 of file reg24le1.h.
| sfr CCH2 = 0xC5 |
Definition at line 77 of file reg24le1.h.
| sfr CCL3 = 0xC6 |
Definition at line 78 of file reg24le1.h.
| sfr CCH3 = 0xC7 |
Definition at line 79 of file reg24le1.h.
| sfr T2CON = 0xC8 |
Definition at line 80 of file reg24le1.h.
| sfr MPAGE = 0xC9 |
Definition at line 81 of file reg24le1.h.
| sfr CRCL = 0xCA |
Definition at line 82 of file reg24le1.h.
| sfr CRCH = 0xCB |
Definition at line 83 of file reg24le1.h.
| sfr TL2 = 0xCC |
Definition at line 84 of file reg24le1.h.
| sfr TH2 = 0xCD |
Definition at line 85 of file reg24le1.h.
| sfr WUOPC1 = 0xCE |
Definition at line 86 of file reg24le1.h.
| sfr WUOPC0 = 0xCF |
Definition at line 87 of file reg24le1.h.
| sfr PSW = 0xD0 |
Definition at line 88 of file reg24le1.h.
| sfr ADCCON3 = 0xD1 |
Definition at line 89 of file reg24le1.h.
| sfr ADCCON2 = 0xD2 |
Definition at line 90 of file reg24le1.h.
| sfr ADCCON1 = 0xD3 |
Definition at line 91 of file reg24le1.h.
| sfr ADCDATH = 0xD4 |
Definition at line 92 of file reg24le1.h.
| sfr ADCDATL = 0xD5 |
Definition at line 93 of file reg24le1.h.
| sfr RNGCTL = 0xD6 |
Definition at line 94 of file reg24le1.h.
| sfr RNGDAT = 0xD7 |
Definition at line 95 of file reg24le1.h.
| sfr ADCON = 0xD8 |
Definition at line 96 of file reg24le1.h.
| sfr W2SADR = 0xD9 |
Definition at line 97 of file reg24le1.h.
| sfr W2DAT = 0xDA |
Definition at line 98 of file reg24le1.h.
| sfr COMPCON = 0xDB |
Definition at line 99 of file reg24le1.h.
| sfr POFCON = 0xDC |
Definition at line 100 of file reg24le1.h.
| sfr CCPDATIA = 0xDD |
Definition at line 101 of file reg24le1.h.
| sfr CCPDATIB = 0xDE |
Definition at line 102 of file reg24le1.h.
| sfr CCPDATO = 0xDF |
Definition at line 103 of file reg24le1.h.
| sfr ACC = 0xE0 |
Definition at line 104 of file reg24le1.h.
| sfr W2CON1 = 0xE1 |
Definition at line 105 of file reg24le1.h.
| sfr W2CON0 = 0xE2 |
Definition at line 106 of file reg24le1.h.
| sfr SPIRCON0 = 0xE4 |
Definition at line 107 of file reg24le1.h.
| sfr SPIRCON1 = 0xE5 |
Definition at line 108 of file reg24le1.h.
| sfr SPIRSTAT = 0xE6 |
Definition at line 109 of file reg24le1.h.
| sfr SPIRDAT = 0xE7 |
Definition at line 110 of file reg24le1.h.
| sfr RFCON = 0xE8 |
Definition at line 111 of file reg24le1.h.
| sfr MD0 = 0xE9 |
Definition at line 112 of file reg24le1.h.
| sfr MD1 = 0xEA |
Definition at line 113 of file reg24le1.h.
| sfr MD2 = 0xEB |
Definition at line 114 of file reg24le1.h.
| sfr MD3 = 0xEC |
Definition at line 115 of file reg24le1.h.
| sfr MD4 = 0xED |
Definition at line 116 of file reg24le1.h.
| sfr MD5 = 0xEE |
Definition at line 117 of file reg24le1.h.
| sfr ARCON = 0xEF |
Definition at line 118 of file reg24le1.h.
| sfr B = 0xF0 |
Definition at line 119 of file reg24le1.h.
| sfr FSR = 0xF8 |
Definition at line 120 of file reg24le1.h.
| sfr FPCR = 0xF9 |
Definition at line 121 of file reg24le1.h.
| sfr FCR = 0xFA |
Definition at line 122 of file reg24le1.h.
| sfr FDCR = 0xFB |
Definition at line 123 of file reg24le1.h.
| sfr SPIMCON0 = 0xFC |
Definition at line 124 of file reg24le1.h.
| sfr SPIMCON1 = 0xFD |
Definition at line 125 of file reg24le1.h.
| sfr SPIMSTAT = 0xFE |
Definition at line 126 of file reg24le1.h.
| sfr SPIMDAT = 0xFF |
Definition at line 127 of file reg24le1.h.
| sfr16 CC1 = 0xC2 |
Definition at line 129 of file reg24le1.h.
| sfr16 CC2 = 0xC4 |
Definition at line 130 of file reg24le1.h.
| sfr16 CC3 = 0xC6 |
Definition at line 131 of file reg24le1.h.
| sfr16 CRC = 0xCA |
Definition at line 132 of file reg24le1.h.
| sfr16 T2 = 0xCC |
Definition at line 133 of file reg24le1.h.
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Definition at line 247 of file reg24le1.h.
Definition at line 248 of file reg24le1.h.
Definition at line 249 of file reg24le1.h.
Definition at line 250 of file reg24le1.h.
Definition at line 253 of file reg24le1.h.
Definition at line 254 of file reg24le1.h.
Definition at line 255 of file reg24le1.h.
Definition at line 258 of file reg24le1.h.
1.7.2