Go to the source code of this file.
Defines | |
| #define | RWD 0x00 |
| #define | WWD 0x08 |
| #define | RGTIMER 0x01 |
| #define | WGTIMER 0x09 |
| #define | RRTCLAT 0x02 |
| #define | WRTCLAT 0x0A |
| #define | RRTC 0x03 |
| #define | WRTCDIS 0x0B |
| #define | RWSTA0 0x04 |
| #define | WWCON0 0x0C |
| #define | RWSTA1 0x05 |
| #define | WWCON1 0x0D |
| #define | INTERRUPT_EXT_INT0 0 |
| #define | INTERRUPT_T0 1 |
| #define | INTERRUPT_AES_RDY 2 |
| #define | INTERRUPT_T1 3 |
| #define | INTERRUPT_UART0 4 |
| #define | INTERRUPT_T2 5 |
| #define | INTERRUPT_RF_RDY 8 |
| #define | INTERRUPT_RFIRQ 9 |
| #define | INTERRUPT_SPI 10 |
| #define | INTERRUPT_USB_WU 11 |
| #define | INTERRUPT_USB_INT 12 |
| #define | INTERRUPT_WU 13 |
Variables | |
| sfr | P0 = 0x80 |
| sfr | SP = 0x81 |
| sfr | DPL = 0x82 |
| sfr | DPH = 0x83 |
| sfr | DPL1 = 0x84 |
| sfr | DPH1 = 0x85 |
| sfr | PCON = 0x87 |
| sfr | TCON = 0x88 |
| sfr | TMOD = 0x89 |
| sfr | TL0 = 0x8A |
| sfr | TL1 = 0x8B |
| sfr | TH0 = 0x8C |
| sfr | TH1 = 0x8D |
| sfr | CKCON = 0x8E |
| sfr | RFCON = 0x90 |
| sfr | DPS = 0x92 |
| sfr | P0DIR = 0x94 |
| sfr | P0ALT = 0x95 |
| sfr | S0CON = 0x98 |
| sfr | S0BUF = 0x99 |
| sfr | IEN2 = 0x9A |
| sfr | USBCON = 0xA0 |
| sfr | CLKCTL = 0xA3 |
| sfr | PWRDWN = 0xA4 |
| sfr | WUCONF = 0xA5 |
| sfr | INTEXP = 0xA6 |
| sfr | IEN0 = 0xA8 |
| sfr | IP0 = 0xA9 |
| sfr | S0RELL = 0xAA |
| sfr | REGXH = 0xAB |
| sfr | REGXL = 0xAC |
| sfr | REGXC = 0xAD |
| sfr | RSTRES = 0xB1 |
| sfr | SMDAT = 0xB2 |
| sfr | SMCTL = 0xB3 |
| sfr | TICKDV = 0xB5 |
| sfr | IEN1 = 0xB8 |
| sfr | IP1 = 0xB9 |
| sfr | S0RELH = 0xBA |
| sfr | SSCONF = 0xBC |
| sfr | SSDATA = 0xBD |
| sfr | SSSTAT = 0xBE |
| sfr | IRCON = 0xC0 |
| sfr | CCEN = 0xC1 |
| sfr | CCL1 = 0xC2 |
| sfr | CCH1 = 0xC3 |
| sfr | CCL2 = 0xC4 |
| sfr | CCH2 = 0xC5 |
| sfr | CCL3 = 0xC6 |
| sfr | CCH3 = 0xC7 |
| sfr | T2CON = 0xC8 |
| sfr | P0EXP = 0xC9 |
| sfr | CRCL = 0xCA |
| sfr | CRCH = 0xCB |
| sfr | TL2 = 0xCC |
| sfr | TH2 = 0xCD |
| sfr | PSW = 0xD0 |
| sfr | WDCON = 0xD8 |
| sfr | USBSLP = 0xD9 |
| sfr | ACC = 0xE0 |
| sfr | RFDAT = 0xE5 |
| sfr | RFCTL = 0xE6 |
| sfr | AESCS = 0xE8 |
| sfr | MD0 = 0xE9 |
| sfr | MD1 = 0xEA |
| sfr | MD2 = 0xEB |
| sfr | MD3 = 0xEC |
| sfr | MD4 = 0xED |
| sfr | MD5 = 0xEE |
| sfr | ARCON = 0xEF |
| sfr | B = 0xF0 |
| sfr | AESKIN = 0xF1 |
| sfr | AESIV = 0xF2 |
| sfr | AESD = 0xF3 |
| sfr | AESIA1 = 0xF5 |
| sfr | AESIA2 = 0xF6 |
| sfr | FSR = 0xF8 |
| sfr | FPCR = 0xF9 |
| sfr | FCR = 0xFA |
| sfr16 | CC1 = 0xC2 |
| sfr16 | CC2 = 0xC4 |
| sfr16 | CC3 = 0xC6 |
| sfr16 | CRC = 0xCA |
| sfr16 | T2 = 0xCC |
| sbit | MCDIS = FSR^7 |
| sbit | STP = FSR^6 |
| sbit | WEN = FSR^5 |
| sbit | RDYN = FSR^4 |
| sbit | INFEN = FSR^3 |
| sbit | RDIS = FSR^2 |
| sbit | RDEND = FSR^1 |
| sbit | WPEN = FSR^0 |
| sbit | CY = PSW^7 |
| sbit | AC = PSW^6 |
| sbit | F0 = PSW^5 |
| sbit | RS1 = PSW^4 |
| sbit | RS0 = PSW^3 |
| sbit | OV = PSW^2 |
| sbit | F1 = PSW^1 |
| sbit | P = PSW^0 |
| sbit | TF1 = TCON^7 |
| sbit | TR1 = TCON^6 |
| sbit | TF0 = TCON^5 |
| sbit | TR0 = TCON^4 |
| sbit | IE1 = TCON^3 |
| sbit | IT1 = TCON^2 |
| sbit | IE0 = TCON^1 |
| sbit | IT0 = TCON^0 |
| sbit | SM0 = S0CON^7 |
| sbit | SM1 = S0CON^6 |
| sbit | SM20 = S0CON^5 |
| sbit | REN0 = S0CON^4 |
| sbit | TB80 = S0CON^3 |
| sbit | RB80 = S0CON^2 |
| sbit | TI0 = S0CON^1 |
| sbit | RI0 = S0CON^0 |
| sbit | T2PS = T2CON^7 |
| sbit | I3FR = T2CON^6 |
| sbit | I2FR = T2CON^5 |
| sbit | T2R1 = T2CON^4 |
| sbit | T2R0 = T2CON^3 |
| sbit | T2CM = T2CON^2 |
| sbit | T2I1 = T2CON^1 |
| sbit | T2I0 = T2CON^0 |
| sbit | EA = IEN0^7 |
| sbit | ET2 = IEN0^5 |
| sbit | ES0 = IEN0^4 |
| sbit | ET1 = IEN0^3 |
| sbit | EX1 = IEN0^2 |
| sbit | ET0 = IEN0^1 |
| sbit | EX0 = IEN0^0 |
| sbit | EXEN2 = IEN1^7 |
| sbit | WUIRQ = IEN1^5 |
| sbit | USB = IEN1^4 |
| sbit | USBWU = IEN1^3 |
| sbit | SPI = IEN1^2 |
| sbit | RF = IEN1^1 |
| sbit | RFSPI = IEN1^0 |
| sbit | EXF2 = IRCON^7 |
| sbit | TF2 = IRCON^6 |
| sbit | WUF = IRCON^5 |
| sbit | USBF = IRCON^4 |
| sbit | USBWUF = IRCON^3 |
| sbit | SPIF = IRCON^2 |
| sbit | RFF = IRCON^1 |
| sbit | RFSPIF = IRCON^0 |
| sbit | SWRST = USBCON^7 |
| sbit | WU = USBCON^6 |
| sbit | SUSPEND = USBCON^5 |
| sbit | IV4 = USBCON^4 |
| sbit | IV3 = USBCON^3 |
| sbit | IV2 = USBCON^2 |
| sbit | IV1 = USBCON^1 |
| sbit | IV0 = USBCON^0 |
| sbit | P00 = P0^0 |
| sbit | P01 = P0^1 |
| sbit | P02 = P0^2 |
| sbit | P03 = P0^3 |
| sbit | MCSN = P0^3 |
| sbit | SCSN = P0^3 |
| sbit | P04 = P0^4 |
| sbit | P05 = P0^5 |
| sbit | RFCE = RFCON^0 |
| sbit | RFCSN = RFCON^1 |
| sbit | RFCKEN = RFCON^2 |
| sbit | BD = WDCON^7 |
| sbit | GO = AESCS^0 |
| sbit | DECR = AESCS^1 |
| #define RWD 0x00 |
Definition at line 236 of file reg24lu1.h.
| #define WWD 0x08 |
Definition at line 237 of file reg24lu1.h.
| #define RGTIMER 0x01 |
Definition at line 238 of file reg24lu1.h.
| #define WGTIMER 0x09 |
Definition at line 239 of file reg24lu1.h.
| #define RRTCLAT 0x02 |
Definition at line 240 of file reg24lu1.h.
| #define WRTCLAT 0x0A |
Definition at line 241 of file reg24lu1.h.
| #define RRTC 0x03 |
Definition at line 242 of file reg24lu1.h.
| #define WRTCDIS 0x0B |
Definition at line 243 of file reg24lu1.h.
| #define RWSTA0 0x04 |
Definition at line 244 of file reg24lu1.h.
| #define WWCON0 0x0C |
Definition at line 245 of file reg24lu1.h.
| #define RWSTA1 0x05 |
Definition at line 246 of file reg24lu1.h.
| #define WWCON1 0x0D |
Definition at line 247 of file reg24lu1.h.
| #define INTERRUPT_EXT_INT0 0 |
Definition at line 253 of file reg24lu1.h.
| #define INTERRUPT_T0 1 |
Definition at line 254 of file reg24lu1.h.
| #define INTERRUPT_AES_RDY 2 |
Definition at line 255 of file reg24lu1.h.
| #define INTERRUPT_T1 3 |
Definition at line 256 of file reg24lu1.h.
| #define INTERRUPT_UART0 4 |
Definition at line 257 of file reg24lu1.h.
| #define INTERRUPT_T2 5 |
Definition at line 258 of file reg24lu1.h.
| #define INTERRUPT_RF_RDY 8 |
Definition at line 259 of file reg24lu1.h.
| #define INTERRUPT_RFIRQ 9 |
Definition at line 260 of file reg24lu1.h.
| #define INTERRUPT_SPI 10 |
Definition at line 261 of file reg24lu1.h.
| #define INTERRUPT_USB_WU 11 |
Definition at line 262 of file reg24lu1.h.
| #define INTERRUPT_USB_INT 12 |
Definition at line 263 of file reg24lu1.h.
| #define INTERRUPT_WU 13 |
Definition at line 264 of file reg24lu1.h.
| sfr P0 = 0x80 |
Definition at line 16 of file reg24lu1.h.
| sfr SP = 0x81 |
Definition at line 17 of file reg24lu1.h.
| sfr DPL = 0x82 |
Definition at line 18 of file reg24lu1.h.
| sfr DPH = 0x83 |
Definition at line 19 of file reg24lu1.h.
| sfr DPL1 = 0x84 |
Definition at line 20 of file reg24lu1.h.
| sfr DPH1 = 0x85 |
Definition at line 21 of file reg24lu1.h.
| sfr PCON = 0x87 |
Definition at line 22 of file reg24lu1.h.
| sfr TCON = 0x88 |
Definition at line 23 of file reg24lu1.h.
| sfr TMOD = 0x89 |
Definition at line 24 of file reg24lu1.h.
| sfr TL0 = 0x8A |
Definition at line 25 of file reg24lu1.h.
| sfr TL1 = 0x8B |
Definition at line 26 of file reg24lu1.h.
| sfr TH0 = 0x8C |
Definition at line 27 of file reg24lu1.h.
| sfr TH1 = 0x8D |
Definition at line 28 of file reg24lu1.h.
| sfr CKCON = 0x8E |
Definition at line 29 of file reg24lu1.h.
| sfr RFCON = 0x90 |
Definition at line 30 of file reg24lu1.h.
| sfr DPS = 0x92 |
Definition at line 31 of file reg24lu1.h.
| sfr P0DIR = 0x94 |
Definition at line 32 of file reg24lu1.h.
| sfr P0ALT = 0x95 |
Definition at line 33 of file reg24lu1.h.
| sfr S0CON = 0x98 |
Definition at line 34 of file reg24lu1.h.
| sfr S0BUF = 0x99 |
Definition at line 35 of file reg24lu1.h.
| sfr IEN2 = 0x9A |
Definition at line 36 of file reg24lu1.h.
| sfr USBCON = 0xA0 |
Definition at line 37 of file reg24lu1.h.
| sfr CLKCTL = 0xA3 |
Definition at line 38 of file reg24lu1.h.
| sfr PWRDWN = 0xA4 |
Definition at line 39 of file reg24lu1.h.
| sfr WUCONF = 0xA5 |
Definition at line 40 of file reg24lu1.h.
| sfr INTEXP = 0xA6 |
Definition at line 41 of file reg24lu1.h.
| sfr IEN0 = 0xA8 |
Definition at line 42 of file reg24lu1.h.
| sfr IP0 = 0xA9 |
Definition at line 43 of file reg24lu1.h.
| sfr S0RELL = 0xAA |
Definition at line 44 of file reg24lu1.h.
| sfr REGXH = 0xAB |
Definition at line 45 of file reg24lu1.h.
| sfr REGXL = 0xAC |
Definition at line 46 of file reg24lu1.h.
| sfr REGXC = 0xAD |
Definition at line 47 of file reg24lu1.h.
| sfr RSTRES = 0xB1 |
Definition at line 48 of file reg24lu1.h.
| sfr SMDAT = 0xB2 |
Definition at line 49 of file reg24lu1.h.
| sfr SMCTL = 0xB3 |
Definition at line 50 of file reg24lu1.h.
| sfr TICKDV = 0xB5 |
Definition at line 51 of file reg24lu1.h.
| sfr IEN1 = 0xB8 |
Definition at line 52 of file reg24lu1.h.
| sfr IP1 = 0xB9 |
Definition at line 53 of file reg24lu1.h.
| sfr S0RELH = 0xBA |
Definition at line 54 of file reg24lu1.h.
| sfr SSCONF = 0xBC |
Definition at line 55 of file reg24lu1.h.
| sfr SSDATA = 0xBD |
Definition at line 56 of file reg24lu1.h.
| sfr SSSTAT = 0xBE |
Definition at line 57 of file reg24lu1.h.
| sfr IRCON = 0xC0 |
Definition at line 58 of file reg24lu1.h.
| sfr CCEN = 0xC1 |
Definition at line 59 of file reg24lu1.h.
| sfr CCL1 = 0xC2 |
Definition at line 60 of file reg24lu1.h.
| sfr CCH1 = 0xC3 |
Definition at line 61 of file reg24lu1.h.
| sfr CCL2 = 0xC4 |
Definition at line 62 of file reg24lu1.h.
| sfr CCH2 = 0xC5 |
Definition at line 63 of file reg24lu1.h.
| sfr CCL3 = 0xC6 |
Definition at line 64 of file reg24lu1.h.
| sfr CCH3 = 0xC7 |
Definition at line 65 of file reg24lu1.h.
| sfr T2CON = 0xC8 |
Definition at line 66 of file reg24lu1.h.
| sfr P0EXP = 0xC9 |
Definition at line 67 of file reg24lu1.h.
| sfr CRCL = 0xCA |
Definition at line 68 of file reg24lu1.h.
| sfr CRCH = 0xCB |
Definition at line 69 of file reg24lu1.h.
| sfr TL2 = 0xCC |
Definition at line 70 of file reg24lu1.h.
| sfr TH2 = 0xCD |
Definition at line 71 of file reg24lu1.h.
| sfr PSW = 0xD0 |
Definition at line 72 of file reg24lu1.h.
| sfr WDCON = 0xD8 |
Definition at line 73 of file reg24lu1.h.
| sfr USBSLP = 0xD9 |
Definition at line 74 of file reg24lu1.h.
| sfr ACC = 0xE0 |
Definition at line 75 of file reg24lu1.h.
| sfr RFDAT = 0xE5 |
Definition at line 76 of file reg24lu1.h.
| sfr RFCTL = 0xE6 |
Definition at line 77 of file reg24lu1.h.
| sfr AESCS = 0xE8 |
Definition at line 78 of file reg24lu1.h.
| sfr MD0 = 0xE9 |
Definition at line 79 of file reg24lu1.h.
| sfr MD1 = 0xEA |
Definition at line 80 of file reg24lu1.h.
| sfr MD2 = 0xEB |
Definition at line 81 of file reg24lu1.h.
| sfr MD3 = 0xEC |
Definition at line 82 of file reg24lu1.h.
| sfr MD4 = 0xED |
Definition at line 83 of file reg24lu1.h.
| sfr MD5 = 0xEE |
Definition at line 84 of file reg24lu1.h.
| sfr ARCON = 0xEF |
Definition at line 85 of file reg24lu1.h.
| sfr B = 0xF0 |
Definition at line 86 of file reg24lu1.h.
| sfr AESKIN = 0xF1 |
Definition at line 87 of file reg24lu1.h.
| sfr AESIV = 0xF2 |
Definition at line 88 of file reg24lu1.h.
| sfr AESD = 0xF3 |
Definition at line 89 of file reg24lu1.h.
| sfr AESIA1 = 0xF5 |
Definition at line 90 of file reg24lu1.h.
| sfr AESIA2 = 0xF6 |
Definition at line 91 of file reg24lu1.h.
| sfr FSR = 0xF8 |
Definition at line 92 of file reg24lu1.h.
| sfr FPCR = 0xF9 |
Definition at line 93 of file reg24lu1.h.
| sfr FCR = 0xFA |
Definition at line 94 of file reg24lu1.h.
| sfr16 CC1 = 0xC2 |
Definition at line 100 of file reg24lu1.h.
| sfr16 CC2 = 0xC4 |
Definition at line 101 of file reg24lu1.h.
| sfr16 CC3 = 0xC6 |
Definition at line 102 of file reg24lu1.h.
| sfr16 CRC = 0xCA |
Definition at line 103 of file reg24lu1.h.
| sfr16 T2 = 0xCC |
Definition at line 104 of file reg24lu1.h.
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1.7.2