00001 /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. 00002 * 00003 * The information contained herein is confidential property of Nordic 00004 * Semiconductor ASA.Terms and conditions of usage are described in detail 00005 * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. 00006 * 00007 * Licensees are granted free, non-transferable use of the information. NO 00008 * WARRENTY of ANY KIND is provided. This heading must NOT be removed from 00009 * the file. 00010 * 00011 * $LastChangedRevision: 133 $ 00012 */ 00013 00018 #include "nrf24le1.h" 00019 #include "hal_spi.h" 00020 #include "nordic_common.h" 00021 00022 void hal_spi_master_init(hal_spi_clkdivider_t ck, hal_spi_mode_t mode, hal_spi_byte_order_t bo) 00023 { 00024 SPIMCON0 = 0; // Default register settings 00025 switch (ck) // Set desired clock divider 00026 { 00027 case SPI_CLK_DIV2: 00028 SPIMCON0 |= (0x00 << 4); 00029 break; 00030 case SPI_CLK_DIV4: 00031 SPIMCON0 |= (0x01 << 4); 00032 break; 00033 case SPI_CLK_DIV8: 00034 SPIMCON0 |= (0x02 << 4); 00035 break; 00036 case SPI_CLK_DIV16: 00037 SPIMCON0 |= (0x03 << 4); 00038 break; 00039 case SPI_CLK_DIV32: 00040 SPIMCON0 |= (0x04 << 4); 00041 break; 00042 case SPI_CLK_DIV64: // We use clock divder 64 as default 00043 default: 00044 SPIMCON0 |= (0x05 << 4); 00045 break; 00046 } 00047 switch(mode) // Set desired mode 00048 { 00049 case HAL_SPI_MODE_0: 00050 SPIMCON0 |= (0x00 << 1); 00051 break; 00052 case HAL_SPI_MODE_1: 00053 SPIMCON0 |= (0x01 << 1); 00054 break; 00055 case HAL_SPI_MODE_2: 00056 SPIMCON0 |= (0x02 << 1); 00057 break; 00058 case HAL_SPI_MODE_3: 00059 SPIMCON0 |= (0x03 << 1); 00060 break; 00061 } 00062 00063 if(bo == HAL_SPI_LSB_MSB) // Set desired data order 00064 { 00065 SPIMCON0 |= BIT_3; 00066 } 00067 00068 SPIMCON0 |= BIT_0; // Enable SPI master 00069 } 00070 00071 uint8_t hal_spi_master_read_write(uint8_t pLoad) 00072 { 00073 SPIMDAT = pLoad ; // Write data to SPI master 00074 while(!(SPIMSTAT & 0x04)) // Wait for data available in rx_fifo 00075 ; 00076 return SPIMDAT; // Return data register 00077 } 00078 00079 void hal_spi_slave_init(hal_spi_mode_t mode, hal_spi_byte_order_t byte_order) 00080 { 00081 uint8_t temp; 00082 SPISCON0 = 0xF0; //default register settings 00083 I3FR=1; 00084 INTEXP |= 0x01; //gate SPI slave interrupt to INT3 00085 00086 switch(mode) 00087 { 00088 case 0: 00089 SPISCON0 |= 0; 00090 break; 00091 case 1: 00092 SPISCON0 |= (1 << 1); 00093 break; 00094 case 2: 00095 SPISCON0 |= (2 << 1); 00096 break; 00097 case 3: 00098 SPISCON0 |= (3 << 1); 00099 break; 00100 } 00101 SPISCON0 |= (~(byte_order & 0x01)) << 3; 00102 00103 //enable SPI slave 00104 SPISCON0 |= 0x01; 00105 while((SPISSTAT & 0x01)) 00106 temp=SPISDAT; //flush rx fifo 00107 } 00108 00109 uint8_t hal_spi_slave_rw(uint8_t pLoad) 00110 { 00111 hal_spi_slave_preload(pLoad); 00112 return hal_spi_slave_read(); 00113 00114 } 00115 00116 uint8_t sstat_shadow = 0; 00117 00118 bool hal_spi_slave_csn_high() 00119 { 00120 static bool csn_high = true; 00121 sstat_shadow |= SPISSTAT; 00122 00123 if(sstat_shadow & 0x20) 00124 { 00125 csn_high = true; 00126 } 00127 else 00128 { 00129 if(sstat_shadow & 0x10) 00130 { 00131 csn_high = false; 00132 } 00133 } 00134 sstat_shadow &= ~0x30; 00135 00136 return csn_high; 00137 } 00138 00139 bool spi_slave_data_ready() 00140 { 00141 sstat_shadow |= SPISSTAT; 00142 00143 if(sstat_shadow & 0x01) 00144 { 00145 return true; 00146 } 00147 else 00148 { 00149 return false; 00150 } 00151 } 00152 00153 uint8_t hal_spi_slave_read() 00154 { 00155 while(!(sstat_shadow & 0x01)) 00156 { 00157 sstat_shadow |= SPISSTAT; 00158 } 00159 sstat_shadow &= ~0x01; 00160 00161 return SPISDAT; 00162 } 00163 00164 void hal_spi_slave_preload(uint8_t pLoad) 00165 { 00166 SPISDAT=pLoad; 00167 }
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